icpld.tan.qmsg

This file is gotten from the web.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 04 16:29:35 2008 " "Info: Processing started: Tue Mar 04 16:29:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off icpld -c icpld --speed=10 " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off icpld -c icpld --speed=10" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "RAM_ADDR_LATCH_OE\$latch~10 " "Warning: Node \"RAM_ADDR_LATCH_OE\$latch~10\"" {  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 27 0 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 27 0 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SWITCH_MODE\[1\] MCU_SEL\[9\] 18.400 ns Longest " "Info: Longest tpd from source pin \"SWITCH_MODE\[1\]\" to destination pin \"MCU_SEL\[9\]\" is 18.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns SWITCH_MODE\[1\] 1 PIN PIN_16 95 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_16; Fanout = 95; PIN Node = 'SWITCH_MODE\[1\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { SWITCH_MODE[1] } "NODE_NAME" } } { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.800 ns) + CELL(1.300 ns) 6.300 ns FREGSEL_LATCH_OE~150 2 COMB LC33 1 " "Info: 2: + IC(3.800 ns) + CELL(1.300 ns) = 6.300 ns; Loc. = LC33; Fanout = 1; COMB Node = 'FREGSEL_LATCH_OE~150'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { SWITCH_MODE[1] FREGSEL_LATCH_OE~150 } "NODE_NAME" } } { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.300 ns) 9.600 ns FREGSEL_LATCH_OE~76 3 COMB LC34 1 " "Info: 3: + IC(0.000 ns) + CELL(3.300 ns) = 9.600 ns; Loc. = LC34; Fanout = 1; COMB Node = 'FREGSEL_LATCH_OE~76'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { FREGSEL_LATCH_OE~150 FREGSEL_LATCH_OE~76 } "NODE_NAME" } } { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 16.800 ns FREGSEL_LATCH_OE~171 4 COMB LC49 1 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 16.800 ns; Loc. = LC49; Fanout = 1; COMB Node = 'FREGSEL_LATCH_OE~171'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "7.200 ns" { FREGSEL_LATCH_OE~76 FREGSEL_LATCH_OE~171 } "NODE_NAME" } } { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 18.400 ns MCU_SEL\[9\] 5 PIN PIN_92 0 " "Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 18.400 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'MCU_SEL\[9\]'" {  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { FREGSEL_LATCH_OE~171 MCU_SEL[9] } "NODE_NAME" } } { "icpld.v" "" { Text "D:/altera/61/quartus/zwork/cpld/icpld.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.400 ns ( 61.96 % ) " "Info: Total cell delay = 11.400 ns ( 61.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.000 ns ( 38.04 % ) " "Info: Total interconnect delay = 7.000 ns ( 38.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "18.400 ns" { SWITCH_MODE[1] FREGSEL_LATCH_OE~150 FREGSEL_LATCH_OE~76 FREGSEL_LATCH_OE~171 MCU_SEL[9] } "NODE_NAME" } } { "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/61/quartus/bin/Technology_Viewer.qrui" "18.400 ns" { SWITCH_MODE[1] SWITCH_MODE[1]~out FREGSEL_LATCH_OE~150 FREGSEL_LATCH_OE~76 FREGSEL_LATCH_OE~171 MCU_SEL[9] } { 0.000ns 0.000ns 3.800ns 0.000ns 3.200ns 0.000ns } { 0.000ns 1.200ns 1.300ns 3.300ns 4.000ns 1.600ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 3 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "98 " "Info: Allocated 98 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 04 16:29:36 2008 " "Info: Processing ended: Tue Mar 04 16:29:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}