📄 icpld.sim.rpt
字号:
; |icpld|MCU_SEL~282 ; |icpld|MCU_SEL~282 ; pexpout ;
; |icpld|MCU_SEL~291 ; |icpld|MCU_SEL~291 ; pexpout ;
; |icpld|MCU_SEL~300 ; |icpld|MCU_SEL~300 ; pexpout ;
; |icpld|MCU_SEL~309 ; |icpld|MCU_SEL~309 ; pexpout ;
; |icpld|MCU_SEL~318 ; |icpld|MCU_SEL~318 ; pexpout ;
; |icpld|MCU_SEL~327 ; |icpld|MCU_SEL~327 ; pexpout ;
; |icpld|RAM_ADDR_LATCH_OE$latch~16 ; |icpld|RAM_ADDR_LATCH_OE$latch~16 ; pexpout ;
; |icpld|RAM_ADDR_LATCH_OE$latch~23 ; |icpld|RAM_ADDR_LATCH_OE$latch~23 ; pexpout ;
; |icpld|SWITCH_MODE[0] ; |icpld|SWITCH_MODE[0] ; dataout ;
; |icpld|SWITCH_MODE[1] ; |icpld|SWITCH_MODE[1] ; dataout ;
; |icpld|SWITCH_MODE[2] ; |icpld|SWITCH_MODE[2] ; dataout ;
; |icpld|MCU_CODE[0] ; |icpld|MCU_CODE[0] ; dataout ;
; |icpld|MCU_CODE[1] ; |icpld|MCU_CODE[1] ; dataout ;
; |icpld|MCU_CODE[2] ; |icpld|MCU_CODE[2] ; dataout ;
; |icpld|MCU_CODE[3] ; |icpld|MCU_CODE[3] ; dataout ;
; |icpld|FPGA_RD ; |icpld|FPGA_RD ; dataout ;
; |icpld|FPGA_WR ; |icpld|FPGA_WR ; dataout ;
; |icpld|EXT_CLK ; |icpld|EXT_CLK ; dataout ;
; |icpld|MCU_CLK ; |icpld|MCU_CLK ; dataout ;
; |icpld|SWCLK ; |icpld|SWCLK ; dataout ;
; |icpld|FPGA2RAM_DATA_DIR ; |icpld|FPGA2RAM_DATA_DIR ; padio ;
; |icpld|FPGA2RAM_DATA_EN ; |icpld|FPGA2RAM_DATA_EN ; padio ;
; |icpld|FPGA2RAM_ADDR_EN ; |icpld|FPGA2RAM_ADDR_EN ; padio ;
; |icpld|RAM_EN[0] ; |icpld|RAM_EN[0] ; padio ;
; |icpld|RAM_EN[1] ; |icpld|RAM_EN[1] ; padio ;
; |icpld|RAM_EN[2] ; |icpld|RAM_EN[2] ; padio ;
; |icpld|RAM_EN[3] ; |icpld|RAM_EN[3] ; padio ;
; |icpld|RAM_OE ; |icpld|RAM_OE ; padio ;
; |icpld|RAM_WR ; |icpld|RAM_WR ; padio ;
; |icpld|FPGA_CLK ; |icpld|FPGA_CLK ; padio ;
; |icpld|FPGA_RESET ; |icpld|FPGA_RESET ; padio ;
; |icpld|MCU_SEL[11] ; |icpld|MCU_SEL[11] ; padio ;
; |icpld|MCU_SEL[0] ; |icpld|MCU_SEL[0] ; padio ;
; |icpld|MCU_SEL[1] ; |icpld|MCU_SEL[1] ; padio ;
; |icpld|MCU_SEL[2] ; |icpld|MCU_SEL[2] ; padio ;
; |icpld|MCU_SEL[3] ; |icpld|MCU_SEL[3] ; padio ;
; |icpld|MCU_SEL[4] ; |icpld|MCU_SEL[4] ; padio ;
; |icpld|MCU_SEL[5] ; |icpld|MCU_SEL[5] ; padio ;
; |icpld|MCU_SEL[6] ; |icpld|MCU_SEL[6] ; padio ;
; |icpld|MCU_SEL[7] ; |icpld|MCU_SEL[7] ; padio ;
; |icpld|MCU_SEL[8] ; |icpld|MCU_SEL[8] ; padio ;
; |icpld|MCU_SEL[9] ; |icpld|MCU_SEL[9] ; padio ;
; |icpld|MCU_SEL[10] ; |icpld|MCU_SEL[10] ; padio ;
; |icpld|RAM_ADDR_LATCH_OE ; |icpld|RAM_ADDR_LATCH_OE ; padio ;
+-----------------------------------+-----------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-------------------------+-------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------+-------------------------+------------------+
; |icpld|always0~48 ; |icpld|always0~48 ; dataout ;
; |icpld|~GND~0 ; |icpld|~GND~0 ; dataout ;
; |icpld|~GND~1 ; |icpld|~GND~1 ; dataout ;
; |icpld|~GND~2 ; |icpld|~GND~2 ; dataout ;
; |icpld|~GND~3 ; |icpld|~GND~3 ; dataout ;
; |icpld|RAM_DATA_SEL[0] ; |icpld|RAM_DATA_SEL[0] ; dataout ;
; |icpld|RAM_DATA_SEL[1] ; |icpld|RAM_DATA_SEL[1] ; dataout ;
; |icpld|RAM_DATA_SEL[2] ; |icpld|RAM_DATA_SEL[2] ; dataout ;
; |icpld|RAM_DATA_SEL[3] ; |icpld|RAM_DATA_SEL[3] ; dataout ;
; |icpld|CPU_RST ; |icpld|CPU_RST ; dataout ;
; |icpld|MCU_RST_CTRL ; |icpld|MCU_RST_CTRL ; dataout ;
; |icpld|MCU_RD ; |icpld|MCU_RD ; dataout ;
; |icpld|MCU_WR ; |icpld|MCU_WR ; dataout ;
; |icpld|FREGSEL_LATCH_OE ; |icpld|FREGSEL_LATCH_OE ; padio ;
; |icpld|DIPCTRL[0] ; |icpld|DIPCTRL[0] ; padio ;
; |icpld|DIPCTRL[1] ; |icpld|DIPCTRL[1] ; padio ;
; |icpld|TXD_CPLD ; |icpld|TXD_CPLD ; padio ;
; |icpld|RAM_DATA_DIR ; |icpld|RAM_DATA_DIR ; padio ;
+-------------------------+-------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------+-------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------+-------------------------+------------------+
; |icpld|always0~48 ; |icpld|always0~48 ; dataout ;
; |icpld|~GND~0 ; |icpld|~GND~0 ; dataout ;
; |icpld|~GND~1 ; |icpld|~GND~1 ; dataout ;
; |icpld|~GND~2 ; |icpld|~GND~2 ; dataout ;
; |icpld|~GND~3 ; |icpld|~GND~3 ; dataout ;
; |icpld|RAM_DATA_SEL[0] ; |icpld|RAM_DATA_SEL[0] ; dataout ;
; |icpld|RAM_DATA_SEL[1] ; |icpld|RAM_DATA_SEL[1] ; dataout ;
; |icpld|RAM_DATA_SEL[2] ; |icpld|RAM_DATA_SEL[2] ; dataout ;
; |icpld|RAM_DATA_SEL[3] ; |icpld|RAM_DATA_SEL[3] ; dataout ;
; |icpld|CPU_RST ; |icpld|CPU_RST ; dataout ;
; |icpld|MCU_RST_CTRL ; |icpld|MCU_RST_CTRL ; dataout ;
; |icpld|MCU_RD ; |icpld|MCU_RD ; dataout ;
; |icpld|MCU_WR ; |icpld|MCU_WR ; dataout ;
; |icpld|FREGSEL_LATCH_OE ; |icpld|FREGSEL_LATCH_OE ; padio ;
; |icpld|DIPCTRL[0] ; |icpld|DIPCTRL[0] ; padio ;
; |icpld|DIPCTRL[1] ; |icpld|DIPCTRL[1] ; padio ;
; |icpld|TXD_CPLD ; |icpld|TXD_CPLD ; padio ;
; |icpld|RAM_DATA_DIR ; |icpld|RAM_DATA_DIR ; padio ;
+-------------------------+-------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Tue Mar 04 15:48:05 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off icpld -c icpld
Info: Using vector source file "D:/altera/61/quartus/zwork/cpld/icpld.vwf"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_DATA_SEL[0]"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_DATA_SEL[1]"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_DATA_SEL[2]"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_DATA_SEL[3]"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_ADDR_LATCH[0]"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_ADDR_LATCH[1]"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_ADDR_LATCH[2]"
Warning: Can't find signal in vector source file for input pin "|icpld|RAM_ADDR_LATCH[3]"
Warning: Can't find signal in vector source file for input pin "|icpld|FREGSEL_LATCH_EN"
Warning: Can't find signal in vector source file for input pin "|icpld|MCU_RD"
Warning: Can't find signal in vector source file for input pin "|icpld|MCU_WR"
Warning: Can't find signal in vector source file for input pin "|icpld|RXD_CPLD"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 80.22 %
Info: Number of transitions in simulation is 4026
Info: Quartus II Simulator was successful. 0 errors, 12 warnings
Info: Allocated 87 megabytes of memory during processing
Info: Processing ended: Tue Mar 04 15:48:06 2008
Info: Elapsed time: 00:00:01
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