mux21a.vhd

来自「EDA课程所用的Max Plus2软件」· VHDL 代码 · 共 20 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21a IS
PORT(a,b: IN STD_LOGIC;
     s:   IN STD_LOGIC;
     y:   OUT STD_LOGIC
    );
END ENTITY mux21a;
ARCHITECTURE one OF mux21a IS
BEGIN
  PROCESS(a,b,s)
    BEGIN
     IF s='0' THEN
        y<=a;
        
     ELSE y<=b;
      END IF;
      END PROCESS;
END ARCHITECTURE one;