fsm_moore.map.qmsg

有关VHDL的Moore状态机程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 26 14:25:04 2006 " "Info: Processing started: Mon Jun 26 14:25:04 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FSM_Moore -c FSM_Moore " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FSM_Moore -c FSM_Moore" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FSM_Moore.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FSM_Moore.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FSM_Moore-behav " "Info: Found design unit 1: FSM_Moore-behav" {  } { { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 FSM_Moore " "Info: Found entity 1: FSM_Moore" {  } { { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FSM_Moore " "Info: Elaborating entity \"FSM_Moore\" for the top level hierarchy" {  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "FSM_Moore.vhd(36) " "Info: VHDL Case Statement information at FSM_Moore.vhd(36): OTHERS choice is never selected" {  } { { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 36 0 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|FSM_Moore\|sreg 5 0 " "Info: State machine \"\|FSM_Moore\|sreg\" contains 5 states and 0 state bits" {  } { { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 12 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|FSM_Moore\|sreg " "Info: Selected Auto state machine encoding method for state machine \"\|FSM_Moore\|sreg\"" {  } { { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 12 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|FSM_Moore\|sreg " "Info: Encoding result for state machine \"\|FSM_Moore\|sreg\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "5 " "Info: Completed encoding using 5 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sreg.a11 " "Info: Encoded state bit \"sreg.a11\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sreg.a00 " "Info: Encoded state bit \"sreg.a00\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sreg.a1 " "Info: Encoded state bit \"sreg.a1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sreg.a0 " "Info: Encoded state bit \"sreg.a0\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "sreg.init " "Info: Encoded state bit \"sreg.init\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Moore\|sreg.init 00000 " "Info: State \"\|FSM_Moore\|sreg.init\" uses code string \"00000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Moore\|sreg.a0 00011 " "Info: State \"\|FSM_Moore\|sreg.a0\" uses code string \"00011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Moore\|sreg.a1 00101 " "Info: State \"\|FSM_Moore\|sreg.a1\" uses code string \"00101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Moore\|sreg.a00 01001 " "Info: State \"\|FSM_Moore\|sreg.a00\" uses code string \"01001\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|FSM_Moore\|sreg.a11 10001 " "Info: State \"\|FSM_Moore\|sreg.a11\" uses code string \"10001\"" {  } {  } 0}  } { { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 12 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "sreg.init High " "Info: Power-up level of register \"sreg.init\" is not specified -- using power-up level of High to minimize register" {  } {  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sreg.init data_in VCC " "Warning: Reduced register \"sreg.init\" with stuck data_in port to stuck value VCC" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "11 " "Info: Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 26 14:25:06 2006 " "Info: Processing ended: Mon Jun 26 14:25:06 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}