fsm_moore.hier_info

有关VHDL的Moore状态机程序

|FSM_Moore
clk => sreg~41.IN1
A => sreg~0.OUTPUTSELECT
A => sreg~1.OUTPUTSELECT
A => sreg~2.OUTPUTSELECT
A => sreg~3.OUTPUTSELECT
A => sreg~4.OUTPUTSELECT
A => process0~0.IN0
A => process0~1.IN0
A => sreg~27.OUTPUTSELECT
A => sreg~28.OUTPUTSELECT
A => sreg~5.OUTPUTSELECT
A => sreg~6.OUTPUTSELECT
A => sreg~7.OUTPUTSELECT
A => sreg~8.OUTPUTSELECT
A => sreg~9.OUTPUTSELECT
A => sreg~10.OUTPUTSELECT
A => sreg~11.OUTPUTSELECT
A => sreg~22.OUTPUTSELECT
A => sreg~23.OUTPUTSELECT
A => sreg~24.OUTPUTSELECT
A => sreg~25.OUTPUTSELECT
A => sreg~26.OUTPUTSELECT
A => process0~3.IN0
A => sreg~29.OUTPUTSELECT
A => sreg~30.OUTPUTSELECT
A => process0~2.IN0
B => process0~1.IN1
B => process0~3.IN1
B => process0~0.IN1
B => process0~2.IN1
Z <= Z~0.DB_MAX_OUTPUT_PORT_TYPE