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📄 fsm_moore.tan.qmsg

📁 有关VHDL的Moore状态机程序
💻 QMSG
📖 第 1 页 / 共 3 页
字号:
🔍
123 
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register sreg.a00 sreg.a11 275.03 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 275.03 MHz between source register \"sreg.a00\" and destination register \"sreg.a11\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.393 ns + Longest register register " "Info: + Longest register to register delay is 1.393 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sreg.a00 1 REG LC_X1_Y19_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { sreg.a00 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.610 ns) + CELL(0.292 ns) 0.902 ns Select~125 2 COMB LC_X1_Y19_N6 1 " "Info: 2: + IC(0.610 ns) + CELL(0.292 ns) = 0.902 ns; Loc. = LC_X1_Y19_N6; Fanout = 1; COMB Node = 'Select~125'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "0.902 ns" { sreg.a00 Select~125 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 1.393 ns sreg.a11 3 REG LC_X1_Y19_N7 4 " "Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 1.393 ns; Loc. = LC_X1_Y19_N7; Fanout = 4; REG Node = 'sreg.a11'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "0.491 ns" { Select~125 sreg.a11 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.601 ns 43.14 % " "Info: Total cell delay = 0.601 ns ( 43.14 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.792 ns 56.86 % " "Info: Total interconnect delay = 0.792 ns ( 56.86 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.393 ns" { sreg.a00 Select~125 sreg.a11 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.393 ns" { sreg.a00 Select~125 sreg.a11 } { 0.000ns 0.610ns 0.182ns } { 0.000ns 0.292ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sreg.a11 2 REG LC_X1_Y19_N7 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N7; Fanout = 4; REG Node = 'sreg.a11'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.485 ns" { clk sreg.a11 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a11 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a11 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sreg.a00 2 REG LC_X1_Y19_N2 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.485 ns" { clk sreg.a00 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a00 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a11 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a11 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a00 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.393 ns" { sreg.a00 Select~125 sreg.a11 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "1.393 ns" { sreg.a00 Select~125 sreg.a11 } { 0.000ns 0.610ns 0.182ns } { 0.000ns 0.292ns 0.309ns } } } { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a11 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a11 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a00 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { sreg.a11 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { sreg.a11 } {  } {  } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sreg.a00 B clk 3.781 ns register " "Info: tsu for register \"sreg.a00\" (data pin = \"B\", clock pin = \"clk\") is 3.781 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.698 ns + Longest pin register " "Info: + Longest pin to register delay is 6.698 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns B 1 PIN PIN_B1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_B1; Fanout = 4; PIN Node = 'B'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { B } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.624 ns) + CELL(0.114 ns) 6.207 ns Select~123 2 COMB LC_X1_Y19_N1 1 " "Info: 2: + IC(4.624 ns) + CELL(0.114 ns) = 6.207 ns; Loc. = LC_X1_Y19_N1; Fanout = 1; COMB Node = 'Select~123'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "4.738 ns" { B Select~123 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.309 ns) 6.698 ns sreg.a00 3 REG LC_X1_Y19_N2 4 " "Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 6.698 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "0.491 ns" { Select~123 sreg.a00 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.892 ns 28.25 % " "Info: Total cell delay = 1.892 ns ( 28.25 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.806 ns 71.75 % " "Info: Total interconnect delay = 4.806 ns ( 71.75 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "6.698 ns" { B Select~123 sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.698 ns" { B B~out0 Select~123 sreg.a00 } { 0.000ns 0.000ns 4.624ns 0.182ns } { 0.000ns 1.469ns 0.114ns 0.309ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } {  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sreg.a00 2 REG LC_X1_Y19_N2 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.485 ns" { clk sreg.a00 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a00 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "6.698 ns" { B Select~123 sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.698 ns" { B B~out0 Select~123 sreg.a00 } { 0.000ns 0.000ns 4.624ns 0.182ns } { 0.000ns 1.469ns 0.114ns 0.309ns } } } { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a00 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Z sreg.a00 7.592 ns register " "Info: tco from clock \"clk\" to destination pin \"Z\" through register \"sreg.a00\" is 7.592 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sreg.a00 2 REG LC_X1_Y19_N2 4 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.485 ns" { clk sreg.a00 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a00 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.414 ns + Longest register pin " "Info: + Longest register to pin delay is 4.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sreg.a00 1 REG LC_X1_Y19_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { sreg.a00 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.607 ns) + CELL(0.590 ns) 1.197 ns Z~0 2 COMB LC_X1_Y19_N5 1 " "Info: 2: + IC(0.607 ns) + CELL(0.590 ns) = 1.197 ns; Loc. = LC_X1_Y19_N5; Fanout = 1; COMB Node = 'Z~0'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.197 ns" { sreg.a00 Z~0 } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.093 ns) + CELL(2.124 ns) 4.414 ns Z 3 PIN PIN_G5 0 " "Info: 3: + IC(1.093 ns) + CELL(2.124 ns) = 4.414 ns; Loc. = PIN_G5; Fanout = 0; PIN Node = 'Z'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "3.217 ns" { Z~0 Z } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.714 ns 61.49 % " "Info: Total cell delay = 2.714 ns ( 61.49 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns 38.51 % " "Info: Total interconnect delay = 1.700 ns ( 38.51 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "4.414 ns" { sreg.a00 Z~0 Z } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.414 ns" { sreg.a00 Z~0 Z } { 0.000ns 0.607ns 1.093ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a00 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a00 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "4.414 ns" { sreg.a00 Z~0 Z } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "4.414 ns" { sreg.a00 Z~0 Z } { 0.000ns 0.607ns 1.093ns } { 0.000ns 0.590ns 2.124ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "sreg.a0 B clk -3.428 ns register " "Info: th for register \"sreg.a0\" (data pin = \"B\", clock pin = \"clk\") is -3.428 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.954 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.954 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_H1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { clk } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.774 ns) + CELL(0.711 ns) 2.954 ns sreg.a0 2 REG LC_X1_Y19_N8 2 " "Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N8; Fanout = 2; REG Node = 'sreg.a0'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "1.485 ns" { clk sreg.a0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 73.80 % " "Info: Total cell delay = 2.180 ns ( 73.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.774 ns 26.20 % " "Info: Total interconnect delay = 0.774 ns ( 26.20 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.397 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.397 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns B 1 PIN PIN_B1 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_B1; Fanout = 4; PIN Node = 'B'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "" { B } "NODE_NAME" } "" } } { "FSM_Moore.vhd" "" { Text "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/FSM_Moore.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.619 ns) + CELL(0.309 ns) 6.397 ns sreg.a0 2 REG LC_X1_Y19_N8 2 " "Info: 2: + IC(4.619 ns) + CELL(0.309 ns) = 6.397 ns; Loc. = LC_X1_Y19_N8; Fanout = 2; REG Node = 'sreg.a0'" {  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "4.928 ns" { B sreg.a0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 27.79 % " "Info: Total cell delay = 1.778 ns ( 27.79 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.619 ns 72.21 % " "Info: Total interconnect delay = 4.619 ns ( 72.21 % )" {  } {  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "6.397 ns" { B sreg.a0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.397 ns" { B B~out0 sreg.a0 } { 0.000ns 0.000ns 4.619ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}  } { { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "2.954 ns" { clk sreg.a0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.954 ns" { clk clk~out0 sreg.a0 } { 0.000ns 0.000ns 0.774ns } { 0.000ns 1.469ns 0.711ns } } } { "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" "" { Report "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore_cmp.qrpt" Compiler "FSM_Moore" "UNKNOWN" "V1" "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/db/FSM_Moore.quartus_db" { Floorplan "L:/可编成逻辑设计软件Quartus II/project\[04\]/FSM_Moore/" "" "6.397 ns" { B sreg.a0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.397 ns" { B B~out0 sreg.a0 } { 0.000ns 0.000ns 4.619ns } { 0.000ns 1.469ns 0.309ns } } }  } 0}
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