fsm_moore.vhd

来自「有关VHDL的Moore状态机程序」· VHDL 代码 · 共 46 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY FSM_Moore IS 
	PORT (clk,A,B: IN STD_LOGIC;
		    Z : OUT STD_LOGIC);
END ENTITY FSM_Moore;

ARCHITECTURE behav OF FSM_Moore IS 

TYPE SREG_TYPE IS (INIT, A0, A1, A00, A11);
SIGNAL sreg: SREG_TYPE;

BEGIN
	PROCESS(clk)
	BEGIN
		IF clk'EVENT AND clk = '1' THEN
		  CASE sreg IS
			WHEN INIT => IF A= '0' THEN sreg <= A0;
									ELSIF A='1' THEN sreg <= A1;
									END IF;
			WHEN A0 =>  IF A='0' THEN sreg <= A00;
									ELSIF A='1' THEN sreg <= A1;
									END IF;
			WHEN A00 => IF A='0' THEN sreg <= A00;
									ELSIF A='1' AND B='0' THEN sreg <= A1;
									ELSIF A='1' AND B='1' THEN sreg <= A11;
									END IF;
			WHEN A1 => IF A='0' THEN sreg <= A0;
									ELSIF A='1' THEN sreg <= A11;
									END IF;
			WHEN A11 => IF A='0' AND B='0' THEN sreg <= A0;
									ELSIF A='0' AND B='1' THEN sreg <= A00;
									ELSIF A='1'THEN sreg <= A11;
									END IF;
			WHEN OTHERS => sreg <= INIT;
		  END CASE;
		END IF;
END PROCESS;

WITH sreg SELECT  ---根据状态决定输出
	Z <= '0' WHEN INIT | A0 | A1,
		 '1' WHEN A00 | A11,
		 '0' WHEN OTHERS;
END ARCHITECTURE behav;