fsm_moore.fit.eqn

有关VHDL的Moore状态机程序

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--sreg.a00 is sreg.a00 at LC_X1_Y19_N2
--operation mode is normal

sreg.a00_lut_out = !A & (sreg.a00 # sreg.a0 # A1L4);
sreg.a00 = DFFEAS(sreg.a00_lut_out, GLOBAL(clk), VCC, , , , , , );


--sreg.a11 is sreg.a11 at LC_X1_Y19_N7
--operation mode is normal

sreg.a11_lut_out = A & (sreg.a1 # sreg.a11 # A1L5);
sreg.a11 = DFFEAS(sreg.a11_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L11 is Z~0 at LC_X1_Y19_N5
--operation mode is normal

A1L11 = sreg.a00 # sreg.a11;


--A1L4 is Select~123 at LC_X1_Y19_N1
--operation mode is normal

A1L4 = sreg.a11 & B;


--sreg.a0 is sreg.a0 at LC_X1_Y19_N8
--operation mode is normal

sreg.a0_lut_out = !A & (sreg.a1 # sreg.a11 & !B);
sreg.a0 = DFFEAS(sreg.a0_lut_out, GLOBAL(clk), VCC, , , , , , );


--A1L5 is Select~125 at LC_X1_Y19_N6
--operation mode is normal

A1L5 = sreg.a00 & B;


--sreg.a1 is sreg.a1 at LC_X1_Y19_N9
--operation mode is normal

sreg.a1_lut_out = A & (sreg.a0 # sreg.a00 & !B);
sreg.a1 = DFFEAS(sreg.a1_lut_out, GLOBAL(clk), VCC, , , , , , );


--B is B at PIN_B1
--operation mode is input

B = INPUT();


--A is A at PIN_C2
--operation mode is input

A = INPUT();


--clk is clk at PIN_H1
--operation mode is input

clk = INPUT();


--Z is Z at PIN_G5
--operation mode is output

Z = OUTPUT(A1L11);