fsm_moore.tan.rpt

有关VHDL的Moore状态机程序

; N/A   ; None         ; 3.770 ns   ; A    ; sreg.a00 ; clk      ;
; N/A   ; None         ; 3.768 ns   ; A    ; sreg.a1  ; clk      ;
; N/A   ; None         ; 3.767 ns   ; A    ; sreg.a11 ; clk      ;
; N/A   ; None         ; 3.766 ns   ; A    ; sreg.a0  ; clk      ;
; N/A   ; None         ; 3.482 ns   ; B    ; sreg.a1  ; clk      ;
; N/A   ; None         ; 3.480 ns   ; B    ; sreg.a0  ; clk      ;
+-------+--------------+------------+------+----------+----------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+----------+----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To ; From Clock ;
+-------+--------------+------------+----------+----+------------+
; N/A   ; None         ; 7.592 ns   ; sreg.a00 ; Z  ; clk        ;
; N/A   ; None         ; 7.292 ns   ; sreg.a11 ; Z  ; clk        ;
+-------+--------------+------------+----------+----+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -3.428 ns ; B    ; sreg.a0  ; clk      ;
; N/A           ; None        ; -3.430 ns ; B    ; sreg.a1  ; clk      ;
; N/A           ; None        ; -3.714 ns ; A    ; sreg.a0  ; clk      ;
; N/A           ; None        ; -3.715 ns ; A    ; sreg.a11 ; clk      ;
; N/A           ; None        ; -3.716 ns ; A    ; sreg.a1  ; clk      ;
; N/A           ; None        ; -3.718 ns ; A    ; sreg.a00 ; clk      ;
; N/A           ; None        ; -3.723 ns ; B    ; sreg.a11 ; clk      ;
; N/A           ; None        ; -3.729 ns ; B    ; sreg.a00 ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Jun 26 14:25:16 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FSM_Moore -c FSM_Moore --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 275.03 MHz between source register "sreg.a00" and destination register "sreg.a11"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.393 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'
            Info: 2: + IC(0.610 ns) + CELL(0.292 ns) = 0.902 ns; Loc. = LC_X1_Y19_N6; Fanout = 1; COMB Node = 'Select~125'
            Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 1.393 ns; Loc. = LC_X1_Y19_N7; Fanout = 4; REG Node = 'sreg.a11'
            Info: Total cell delay = 0.601 ns ( 43.14 % )
            Info: Total interconnect delay = 0.792 ns ( 56.86 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N7; Fanout = 4; REG Node = 'sreg.a11'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
            Info: - Longest clock path from clock "clk" to source register is 2.954 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'
                Info: Total cell delay = 2.180 ns ( 73.80 % )
                Info: Total interconnect delay = 0.774 ns ( 26.20 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tsu for register "sreg.a00" (data pin = "B", clock pin = "clk") is 3.781 ns
    Info: + Longest pin to register delay is 6.698 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_B1; Fanout = 4; PIN Node = 'B'
        Info: 2: + IC(4.624 ns) + CELL(0.114 ns) = 6.207 ns; Loc. = LC_X1_Y19_N1; Fanout = 1; COMB Node = 'Select~123'
        Info: 3: + IC(0.182 ns) + CELL(0.309 ns) = 6.698 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'
        Info: Total cell delay = 1.892 ns ( 28.25 % )
        Info: Total interconnect delay = 4.806 ns ( 71.75 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
Info: tco from clock "clk" to destination pin "Z" through register "sreg.a00" is 7.592 ns
    Info: + Longest clock path from clock "clk" to source register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.414 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y19_N2; Fanout = 4; REG Node = 'sreg.a00'
        Info: 2: + IC(0.607 ns) + CELL(0.590 ns) = 1.197 ns; Loc. = LC_X1_Y19_N5; Fanout = 1; COMB Node = 'Z~0'
        Info: 3: + IC(1.093 ns) + CELL(2.124 ns) = 4.414 ns; Loc. = PIN_G5; Fanout = 0; PIN Node = 'Z'
        Info: Total cell delay = 2.714 ns ( 61.49 % )
        Info: Total interconnect delay = 1.700 ns ( 38.51 % )
Info: th for register "sreg.a0" (data pin = "B", clock pin = "clk") is -3.428 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.954 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_H1; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.774 ns) + CELL(0.711 ns) = 2.954 ns; Loc. = LC_X1_Y19_N8; Fanout = 2; REG Node = 'sreg.a0'
        Info: Total cell delay = 2.180 ns ( 73.80 % )
        Info: Total interconnect delay = 0.774 ns ( 26.20 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 6.397 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_B1; Fanout = 4; PIN Node = 'B'
        Info: 2: + IC(4.619 ns) + CELL(0.309 ns) = 6.397 ns; Loc. = LC_X1_Y19_N8; Fanout = 2; REG Node = 'sreg.a0'
        Info: Total cell delay = 1.778 ns ( 27.79 % )
        Info: Total interconnect delay = 4.619 ns ( 72.21 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Jun 26 14:25:16 2006
    Info: Elapsed time: 00:00:01