fsm_moore.map.rpt

有关VHDL的Moore状态机程序

; Analysis & Synthesis Source Files Read                                                                                                     ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                        ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+
; FSM_Moore.vhd                    ; yes             ; User VHDL File  ; L:/可编成逻辑设计软件Quartus II/project[04]/FSM_Moore/FSM_Moore.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------+-----------+
; Resource                        ; Usage     ;
+---------------------------------+-----------+
; Total logic elements            ; 7         ;
; Total combinational functions   ; 7         ;
;     -- Total 4-input functions  ; 4         ;
;     -- Total 3-input functions  ; 0         ;
;     -- Total 2-input functions  ; 3         ;
;     -- Total 1-input functions  ; 0         ;
;     -- Total 0-input functions  ; 0         ;
; Combinational cells for routing ; 0         ;
; Total registers                 ; 4         ;
; I/O pins                        ; 4         ;
; Maximum fan-out node            ; sreg.a00  ;
; Maximum fan-out                 ; 4         ;
; Total fan-out                   ; 27        ;
; Average fan-out                 ; 2.45      ;
+---------------------------------+-----------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |FSM_Moore                 ; 7 (7)       ; 4            ; 0           ; 4    ; 0            ; 3 (3)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; |FSM_Moore          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------------------+
; State Machine - |FSM_Moore|sreg                                 ;
+-----------+----------+----------+---------+---------+-----------+
; Name      ; sreg.a11 ; sreg.a00 ; sreg.a1 ; sreg.a0 ; sreg.init ;
+-----------+----------+----------+---------+---------+-----------+
; sreg.init ; 0        ; 0        ; 0       ; 0       ; 0         ;
; sreg.a0   ; 0        ; 0        ; 0       ; 1       ; 1         ;
; sreg.a1   ; 0        ; 0        ; 1       ; 0       ; 1         ;
; sreg.a00  ; 0        ; 1        ; 0       ; 0       ; 1         ;
; sreg.a11  ; 1        ; 0        ; 0       ; 0       ; 1         ;
+-----------+----------+----------+---------+---------+-----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in L:/可编成逻辑设计软件Quartus II/project[04]/FSM_Moore/FSM_Moore.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Mon Jun 26 14:25:04 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FSM_Moore -c FSM_Moore
Info: Found 2 design units, including 1 entities, in source file FSM_Moore.vhd
    Info: Found design unit 1: FSM_Moore-behav
    Info: Found entity 1: FSM_Moore
Info: Elaborating entity "FSM_Moore" for the top level hierarchy
Info: VHDL Case Statement information at FSM_Moore.vhd(36): OTHERS choice is never selected
Info: State machine "|FSM_Moore|sreg" contains 5 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|FSM_Moore|sreg"
Info: Encoding result for state machine "|FSM_Moore|sreg"
    Info: Completed encoding using 5 state bits
        Info: Encoded state bit "sreg.a11"
        Info: Encoded state bit "sreg.a00"
        Info: Encoded state bit "sreg.a1"
        Info: Encoded state bit "sreg.a0"
        Info: Encoded state bit "sreg.init"
    Info: State "|FSM_Moore|sreg.init" uses code string "00000"
    Info: State "|FSM_Moore|sreg.a0" uses code string "00011"
    Info: State "|FSM_Moore|sreg.a1" uses code string "00101"
    Info: State "|FSM_Moore|sreg.a00" uses code string "01001"
    Info: State "|FSM_Moore|sreg.a11" uses code string "10001"
Info: Power-up level of register "sreg.init" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "sreg.init" with stuck data_in port to stuck value VCC
Info: Implemented 11 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 1 output pins
    Info: Implemented 7 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Mon Jun 26 14:25:06 2006
    Info: Elapsed time: 00:00:03