fsm_moore.fit.summary

有关VHDL的Moore状态机程序

Flow Status : Successful - Mon Jun 26 14:25:11 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : FSM_Moore
Top-level Entity Name : FSM_Moore
Family : Cyclone
Device : EP1C6F256C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 7 / 5,980 ( < 1 % )
Total pins : 4 / 185 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )