la_usb-spi.vhd

有关到SRAM的VHDL程序,也涉及到USB接口

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity d_out is
    Port ( RST : in std_logic;
			  clk : in std_logic;
           reset : in std_logic;
--USB GPIF INTERFACE
          -- USB_XCLK : in std_logic;
           USB_RDY : out std_logic_vector(1 downto 0);
           USB_CTRL : in std_logic_vector(1 downto 0);
           USB_XDATA : inout std_logic_vector(15 downto 0);
--USB OTHER
           USB_PA0 : in std_logic;
           USB_PA1 : in std_logic;
           --USB_PA2 : in std_logic;
           LA_IN   : in std_logic_vector(15 downto 0);
			  usb_IFCLK:in std_logic;
--SRAM INTERFACE
           SRAM_CS : out std_logic;
           SRAM_OE : out std_logic;
           SRAM_WE : out std_logic;
           SRAM_ADDR : out std_logic_vector(15 downto 0);
           SRAM_Data : inout std_logic_vector(15 downto 0);
		     
			  SRAM2_OE: out std_logic;
           SRAM2_WE: out std_logic;
           SRAM2_CS: out std_logic;
           SRAM2_ADDR:out std_logic_vector(15 downto 0);
           SRAM2_Data:inout std_logic_vector(15 downto 0);
--OUTPUT 
			  --S_OUT0 : out std_logic;
			  --S_OUT1 : out std_logic;
			  LED : out std_logic;
			  STAS0 : out std_logic;
--SPI
           SPI_SCK: in std_logic;	  
			  SPI_SS:  in std_logic;	
		     SPI_MOSI:in std_logic
		);
end d_out;

architecture d_out_arch of d_out is

--control signal
signal  DO_RUN_OUT:std_logic; --:= '0'
signal  DO_RUN_IN:std_logic; 
signal  DO_WORK: std_logic;
--spi signal 
signal shift_reg: STD_LOGIC_VECTOR (31 downto 0);
signal shift_cnt: STD_LOGIC_VECTOR (4 downto 0);
signal buf_reg,dmd_timer: STD_LOGIC_VECTOR (15 downto 0);
signal shift_clk: std_logic;


--SRAM interface
signal SRAM_RD_CLK,SRAM_WR_CLK:std_logic;
signal SRAM_ADDR_RD:std_logic_vector(16 downto 0);
signal SRAM_ADDR_WR:std_logic_vector(16 downto 0);
signal WRITE_OK,READ_OK:std_logic;		

--WORK CONTROL STATE MACHINE				 
type WORK_states is(WORK_idle,WORK_WRITE_EN,WORK_READ_EN);
signal WORK_CURRENT_STATE,WORK_NEXT_STATE: WORK_states;
signal WR_EN,sWR_EN:std_logic;
signal RD_EN,sRD_EN:std_logic;		

-----------------------------------------------------------------------------------------------------
begin

process(clk) ----------copy Shift register--------------,USB_PA0,USB_PA1
begin
      if (clk'event and clk ='1') then
			DO_RUN_OUT <=USB_PA0; --RUN/STOP OF OUTPUT
			DO_RUN_IN <=USB_PA1; --RUN/STOP OF INPUT
			buf_reg <= buf_reg+1;
			end if;
end process;
STAS0<=DO_RUN_OUT;

--reset <= USB_PA0; --Soft reset
--S_OUT0 <= USB_CTRL(0);
--S_OUT1 <= USB_CTRL(1);
--****************************************************************************************************
--************************************    SRAM INTERFACE    ****************************************
--****************************************************************************************************
SRAM_CS <= not DO_WORK;
SRAM_WR_CLK <= clk  ;
--SRAM_WR_CLK <= USB_CTRL(0) AND RST;--USB_CTRL(0) OR USB_XCLK;--
SRAM_RD_CLK <= USB_CTRL(1)or (not usb_IFCLK);--USB_CTRL(2) OR (not USB_XCLK);--


----********************** 	SPI INTERFACE					*******************************
--*****************************************************************************************
shift_clk<=SPI_SCK and rst;

sr_proc : process(shift_clk,SPI_SS) -------------Shift register----------------
  begin
      if (SPI_SS='1') then
        shift_reg <= (others=>'0');   -- sync reset
		shift_cnt<=(others=>'0');
      elsif (shift_clk'event and shift_clk ='1') then
          shift_reg <= shift_reg(30 downto 0) & SPI_MOSI;
		  shift_cnt<=shift_cnt+1;
      end if;
end process sr_proc;

cs_proc : process(clk,shift_cnt) ----------copy Shift register--------------
  begin
      if (clk'event and clk ='1') then
	  	if(shift_cnt(4)='1') then
	      --  buf_reg <= shift_reg(15 downto 0);
		end if;
      end if;
end process cs_proc;


--SRAM address generator
SRAM_ADDR_RD_GEN:process(RD_EN,SRAM_RD_CLK)
begin
	if(RD_EN ='0') then SRAM_ADDR_RD <=(others =>'0');
	elsif(SRAM_RD_CLK'event and SRAM_RD_CLK='1')then 
		SRAM_ADDR_RD<=SRAM_ADDR_RD +1;  --SRAM ADDRESS 
	end if;
end process SRAM_ADDR_RD_GEN;
READ_OK<=SRAM_ADDR_RD(16);

SRAM_ADDR_WR_GEN:process(WR_EN,SRAM_WR_CLK )  
begin
	if(WR_EN ='0') then SRAM_ADDR_WR <=(others =>'0');
	elsif(SRAM_WR_CLK' event and SRAM_WR_CLK='1'  )then      
		SRAM_ADDR_WR<=SRAM_ADDR_WR +1;  --SRAM ADDRESS 
	end if;
end process SRAM_ADDR_WR_GEN;
WRITE_OK<=SRAM_ADDR_WR(16);

SRAM_ADDR<=SRAM_ADDR_RD(15 DOWNTO 0)WHEN(RD_EN='1') ELSE SRAM_ADDR_WR(15 DOWNTO 0);
SRAM_OE <= SRAM_RD_CLK   WHEN(RD_EN ='1' and DO_WORK ='1') ELSE '1'; --READ SRAM1
                             --WR_EN = '1'
SRAM_WE <= SRAM_WR_CLK WHEN(WR_EN ='1' and DO_WORK ='1') ELSE '1'; --write SRAM1
--USB_XDATA(15 DOWNTO 0)    buf_reg         RD_EN = '0' and DO_WORK ='1'
                                                          -- WR_EN = '1'
SRAM_Data <=SRAM_ADDR_WR(15 DOWNTO 0)  WHEN(DO_WORK ='1' and WR_EN ='1'  ) ELSE "ZZZZZZZZZZZZZZZZ";
USB_XDATA <= SRAM_data WHEN(RD_EN ='1' and DO_WORK ='1') ELSE "ZZZZZZZZZZZZZZZZ";
                         --  DO_WORK<='1' and RD_EN<='1'

--SRAM_WE <= SRAM_WR_CLK WHEN(RD_EN = '0' and DO_WORK ='1') ELSE '1'; --write SRAM1
--SRAM_Data <=SRAM_ADDR_WR(15 DOWNTO 0) WHEN(RD_EN = '0' and DO_WORK ='1') ELSE "ZZZZZZZZZZZZZZZZ";
--****************************************************************************************************
--************************************    FSM CONTROL    **********************************************
--****************************************************************************************************
USB_RDY(0)<=RD_EN;
          
          
--switch State
WORK_Switch_state:process(RST,clk,WORK_NEXT_STATE,reset)
begin             
	if(RST = '0' or reset ='0' )then
		WR_EN<='0';
		RD_EN<='0';
		
		
		WORK_CURRENT_STATE <= WORK_idle;
	elsif(clk'event and clk = '1')then 
		WR_EN<=sWR_EN;
		RD_EN<=sRD_EN;
		WORK_CURRENT_STATE <= WORK_NEXT_STATE;
		end if;
end process WORK_Switch_state;


--Change state
WORK_Change_state:process(WORK_CURRENT_STATE,DO_RUN_OUT,DO_RUN_IN,WRITE_OK,READ_OK)
begin
   
	DO_WORK<='0';
	sWR_EN<='0';
	sRD_EN<='0';
	LED<='1';
	case WORK_CURRENT_STATE is
		when WORK_idle	=>
							if(DO_RUN_OUT ='1') then WORK_NEXT_STATE	<= WORK_WRITE_EN;
							elsif(DO_RUN_IN ='1') then WORK_NEXT_STATE	<= WORK_READ_EN;
							else WORK_NEXT_STATE	<= WORK_idle;
							end if;

		when WORK_WRITE_EN	=>	DO_WORK <='1';sWR_EN <='1';LED<='1';
							if(WRITE_OK = '1') then WORK_NEXT_STATE	<= WORK_idle;
							else WORK_NEXT_STATE	<= WORK_WRITE_EN;
							end if;

		when WORK_READ_EN	=>	DO_WORK<='1';sRD_EN<='1';LED<='0';
							if(READ_OK = '1') then WORK_NEXT_STATE	<= WORK_idle;
							                        
							else WORK_NEXT_STATE	<= WORK_READ_EN;
							end if;

		when others	=> WORK_NEXT_STATE	<= WORK_idle;
	end case;
end process WORK_Change_state;

end d_out_arch;