de2_lcm_test.fit.qmsg

DE2彩色LCM的Demo测试程序.包括DE2接口和驱动程序

{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "LCM_PLL:u0\|altpll:altpll_component\|pll clk\[0\] GPIO_0\[29\] " "Warning: PLL \"LCM_PLL:u0\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"GPIO_0\[29\]\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "LCM_PLL.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/LCM_PLL.v" 79 -1 0 } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 395 -1 0 } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 295 -1 0 } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}