de2_lcm_test.tan.qmsg

来自「DE2彩色LCM的Demo测试程序.包括DE2接口和驱动程序」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITDB_FULL_SLACK_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 register H_Cont\[5\] register MOD_3\[0\] 50.338 ns " "Info: Slack time is 50.338 ns for clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" between source register \"H_Cont\[5\]\" and destination register \"MOD_3\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "253.36 MHz 3.947 ns " "Info: Fmax is 253.36 MHz (period= 3.947 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "54.070 ns + Largest register register " "Info: + Largest register to register requirement is 54.070 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "54.285 ns + " "Info: + Setup relationship between source and destination is 54.285 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 51.927 ns " "Info: + Latch edge is 51.927 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns  50 " "Info: Clock period of Destination clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -2.358 ns " "Info: - Launch edge is -2.358 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source LCM_PLL:u0\|altpll:altpll_component\|_clk0 54.285 ns -2.358 ns  50 " "Info: Clock period of Source clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" is 54.285 ns with  offset of -2.358 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns + Largest " "Info: + Largest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 destination 2.649 ns + Shortest register " "Info: + Shortest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to destination register is 2.649 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 35 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.537 ns) 2.649 ns MOD_3\[0\] 3 REG LCFF_X57_Y23_N3 3 " "Info: 3: + IC(1.021 ns) + CELL(0.537 ns) = 2.649 ns; Loc. = LCFF_X57_Y23_N3; Fanout = 3; REG Node = 'MOD_3\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.558 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 401 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.27 % ) " "Info: Total cell delay = 0.537 ns ( 20.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.112 ns ( 79.73 % ) " "Info: Total interconnect delay = 2.112 ns ( 79.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LCM_PLL:u0\|altpll:altpll_component\|_clk0 source 2.650 ns - Longest register " "Info: - Longest clock path from clock \"LCM_PLL:u0\|altpll:altpll_component\|_clk0\" to source register is 2.650 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { LCM_PLL:u0|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.091 ns) + CELL(0.000 ns) 1.091 ns LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 35 " "Info: 2: + IC(1.091 ns) + CELL(0.000 ns) = 1.091 ns; Loc. = CLKCTRL_G3; Fanout = 35; COMB Node = 'LCM_PLL:u0\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.091 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "e:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.022 ns) + CELL(0.537 ns) 2.650 ns H_Cont\[5\] 3 REG LCFF_X58_Y23_N11 6 " "Info: 3: + IC(1.022 ns) + CELL(0.537 ns) = 2.650 ns; Loc. = LCFF_X58_Y23_N11; Fanout = 6; REG Node = 'H_Cont\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.559 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 427 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.537 ns ( 20.26 % ) " "Info: Total cell delay = 0.537 ns ( 20.26 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.113 ns ( 79.74 % ) " "Info: Total interconnect delay = 2.113 ns ( 79.74 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 427 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 401 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.732 ns - Longest register register " "Info: - Longest register to register delay is 3.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns H_Cont\[5\] 1 REG LCFF_X58_Y23_N11 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X58_Y23_N11; Fanout = 6; REG Node = 'H_Cont\[5\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { H_Cont[5] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 427 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.736 ns) + CELL(0.420 ns) 1.156 ns always0~178 2 COMB LCCOMB_X58_Y23_N24 1 " "Info: 2: + IC(0.736 ns) + CELL(0.420 ns) = 1.156 ns; Loc. = LCCOMB_X58_Y23_N24; Fanout = 1; COMB Node = 'always0~178'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.156 ns" { H_Cont[5] always0~178 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.711 ns) + CELL(0.275 ns) 2.142 ns always0~180 3 COMB LCCOMB_X58_Y24_N2 1 " "Info: 3: + IC(0.711 ns) + CELL(0.275 ns) = 2.142 ns; Loc. = LCCOMB_X58_Y24_N2; Fanout = 1; COMB Node = 'always0~180'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.986 ns" { always0~178 always0~180 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(0.150 ns) 2.532 ns always0~179 4 COMB LCCOMB_X58_Y24_N0 10 " "Info: 4: + IC(0.240 ns) + CELL(0.150 ns) = 2.532 ns; Loc. = LCCOMB_X58_Y24_N0; Fanout = 10; COMB Node = 'always0~179'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.390 ns" { always0~180 always0~179 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.740 ns) + CELL(0.376 ns) 3.648 ns MOD_3~163 5 COMB LCCOMB_X57_Y23_N2 1 " "Info: 5: + IC(0.740 ns) + CELL(0.376 ns) = 3.648 ns; Loc. = LCCOMB_X57_Y23_N2; Fanout = 1; COMB Node = 'MOD_3~163'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.116 ns" { always0~179 MOD_3~163 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 397 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.732 ns MOD_3\[0\] 6 REG LCFF_X57_Y23_N3 3 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 3.732 ns; Loc. = LCFF_X57_Y23_N3; Fanout = 3; REG Node = 'MOD_3\[0\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { MOD_3~163 MOD_3[0] } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 401 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.305 ns ( 34.97 % ) " "Info: Total cell delay = 1.305 ns ( 34.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.427 ns ( 65.03 % ) " "Info: Total interconnect delay = 2.427 ns ( 65.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.732 ns" { H_Cont[5] always0~178 always0~180 always0~179 MOD_3~163 MOD_3[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.732 ns" { H_Cont[5] always0~178 always0~180 always0~179 MOD_3~163 MOD_3[0] } { 0.000ns 0.736ns 0.711ns 0.240ns 0.740ns 0.000ns } { 0.000ns 0.420ns 0.275ns 0.150ns 0.376ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.649 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl MOD_3[0] } { 0.000ns 1.091ns 1.021ns } { 0.000ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "2.650 ns" { LCM_PLL:u0|altpll:altpll_component|_clk0 LCM_PLL:u0|altpll:altpll_component|_clk0~clkctrl H_Cont[5] } { 0.000ns 1.091ns 1.022ns } { 0.000ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.732 ns" { H_Cont[5] always0~178 always0~180 always0~179 MOD_3~163 MOD_3[0] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "3.732 ns" { H_Cont[5] always0~178 always0~180 always0~179 MOD_3~163 MOD_3[0] } { 0.000ns 0.736ns 0.711ns 0.240ns 0.740ns 0.000ns } { 0.000ns 0.420ns 0.275ns 0.150ns 0.376ns 0.084ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CLOCK_50 register I2S_LCM_Config:u4\|mI2S_DATA\[12\] register I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA 8.054 ns " "Info: Slack time is 8.054 ns for clock \"CLOCK_50\" between source register \"I2S_LCM_Config:u4\|mI2S_DATA\[12\]\" and destination register \"I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "256.94 MHz 3.892 ns " "Info: Fmax is 256.94 MHz (period= 3.892 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.786 ns + Largest register register " "Info: + Largest register to register requirement is 9.786 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "10.000 ns + " "Info: + Setup relationship between source and destination is 10.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 10.000 ns " "Info: + Latch edge is 10.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CLOCK_50 20.000 ns 10.000 ns inverted 50 " "Info: Clock period of Destination clock \"CLOCK_50\" is 20.000 ns with inverted offset of 10.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CLOCK_50 20.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CLOCK_50\" is 20.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 6.093 ns + Shortest register " "Info: + Shortest clock path from clock \"CLOCK_50\" to destination register is 6.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.787 ns) 2.922 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK 3 REG LCFF_X58_Y24_N29 3 " "Info: 3: + IC(1.018 ns) + CELL(0.787 ns) = 2.922 ns; Loc. = LCFF_X58_Y24_N29; Fanout = 3; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.805 ns" { CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.000 ns) 4.547 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl 4 COMB CLKCTRL_G7 30 " "Info: 4: + IC(1.625 ns) + CELL(0.000 ns) = 4.547 ns; Loc. = CLKCTRL_G7; Fanout = 30; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.625 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.537 ns) 6.093 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA 5 REG LCFF_X62_Y23_N9 1 " "Info: 5: + IC(1.009 ns) + CELL(0.537 ns) = 6.093 ns; Loc. = LCFF_X62_Y23_N9; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.546 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 38.13 % ) " "Info: Total cell delay = 2.323 ns ( 38.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.770 ns ( 61.87 % ) " "Info: Total interconnect delay = 3.770 ns ( 61.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 source 6.093 ns - Longest register " "Info: - Longest clock path from clock \"CLOCK_50\" to source register is 6.093 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'CLOCK_50'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 17 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 17; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "DE2_LCM_Test.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/DE2_LCM_Test.v" 174 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.787 ns) 2.922 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK 3 REG LCFF_X58_Y24_N29 3 " "Info: 3: + IC(1.018 ns) + CELL(0.787 ns) = 2.922 ns; Loc. = LCFF_X58_Y24_N29; Fanout = 3; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.805 ns" { CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.625 ns) + CELL(0.000 ns) 4.547 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl 4 COMB CLKCTRL_G7 30 " "Info: 4: + IC(1.625 ns) + CELL(0.000 ns) = 4.547 ns; Loc. = CLKCTRL_G7; Fanout = 30; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mI2S_CLK~clkctrl'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.625 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.537 ns) 6.093 ns I2S_LCM_Config:u4\|mI2S_DATA\[12\] 5 REG LCFF_X62_Y23_N1 1 " "Info: 5: + IC(1.009 ns) + CELL(0.537 ns) = 6.093 ns; Loc. = LCFF_X62_Y23_N1; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|mI2S_DATA\[12\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.546 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_LCM_Config.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 38.13 % ) " "Info: Total cell delay = 2.323 ns ( 38.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.770 ns ( 61.87 % ) " "Info: Total interconnect delay = 3.770 ns ( 61.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "I2S_LCM_Config.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_LCM_Config.v" 44 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 71 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.732 ns - Longest register register " "Info: - Longest register to register delay is 1.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns I2S_LCM_Config:u4\|mI2S_DATA\[12\] 1 REG LCFF_X62_Y23_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X62_Y23_N1; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|mI2S_DATA\[12\]'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "I2S_LCM_Config.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_LCM_Config.v" 44 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.150 ns) 0.455 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~370 2 COMB LCCOMB_X62_Y23_N22 1 " "Info: 2: + IC(0.305 ns) + CELL(0.150 ns) = 0.455 ns; Loc. = LCCOMB_X62_Y23_N22; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~370'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.455 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.249 ns) + CELL(0.150 ns) 0.854 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~371 3 COMB LCCOMB_X62_Y23_N10 1 " "Info: 3: + IC(0.249 ns) + CELL(0.150 ns) = 0.854 ns; Loc. = LCCOMB_X62_Y23_N10; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~371'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.399 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 1.251 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~372 4 COMB LCCOMB_X62_Y23_N6 1 " "Info: 4: + IC(0.247 ns) + CELL(0.150 ns) = 1.251 ns; Loc. = LCCOMB_X62_Y23_N6; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~372'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.150 ns) 1.648 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~375 5 COMB LCCOMB_X62_Y23_N8 1 " "Info: 5: + IC(0.247 ns) + CELL(0.150 ns) = 1.648 ns; Loc. = LCCOMB_X62_Y23_N8; Fanout = 1; COMB Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|Mux0~375'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.397 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 128 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.732 ns I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA 6 REG LCFF_X62_Y23_N9 1 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 1.732 ns; Loc. = LCFF_X62_Y23_N9; Fanout = 1; REG Node = 'I2S_LCM_Config:u4\|I2S_Controller:u0\|mSDATA'" {  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "I2S_Controller.v" "" { Text "F:/EDA/DE2/DE2_LCM/DE2_LCM_Test/I2S_Controller.v" 71 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.684 ns ( 39.49 % ) " "Info: Total cell delay = 0.684 ns ( 39.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.048 ns ( 60.51 % ) " "Info: Total interconnect delay = 1.048 ns ( 60.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.732 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.732 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.305ns 0.249ns 0.247ns 0.247ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.150ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.093 ns" { CLOCK_50 CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "6.093 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK I2S_LCM_Config:u4|I2S_Controller:u0|mI2S_CLK~clkctrl I2S_LCM_Config:u4|mI2S_DATA[12] } { 0.000ns 0.000ns 0.118ns 1.018ns 1.625ns 1.009ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.732 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } "NODE_NAME" } } { "e:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/quartus60/win/Technology_Viewer.qrui" "1.732 ns" { I2S_LCM_Config:u4|mI2S_DATA[12] I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~370 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~371 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~372 I2S_LCM_Config:u4|I2S_Controller:u0|Mux0~375 I2S_LCM_Config:u4|I2S_Controller:u0|mSDATA } { 0.000ns 0.305ns 0.249ns 0.247ns 0.247ns 0.000ns } { 0.000ns 0.150ns 0.150ns 0.150ns 0.150ns 0.084ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}