de2_lcm_test.v

DE2彩色LCM的Demo测试程序.包括DE2接口和驱动程序

inout	[7:0]	LCD_DATA;				//	LCD Data bus 8 bits
output			LCD_ON;					//	LCD Power ON/OFF
output			LCD_BLON;				//	LCD Back Light ON/OFF
output			LCD_RW;					//	LCD Read/Write Select, 0 = Write, 1 = Read
output			LCD_EN;					//	LCD Enable
output			LCD_RS;					//	LCD Command/Data Select, 0 = Command, 1 = Data
////////////////////	SD Card Interface	////////////////////////
inout			SD_DAT;					//	SD Card Data
inout			SD_DAT3;				//	SD Card Data 3
inout			SD_CMD;					//	SD Card Command Signal
output			SD_CLK;					//	SD Card Clock
////////////////////////	I2C		////////////////////////////////
inout			I2C_SDAT;				//	I2C Data
output			I2C_SCLK;				//	I2C Clock
////////////////////////	PS2		////////////////////////////////
input		 	PS2_DAT;				//	PS2 Data
input			PS2_CLK;				//	PS2 Clock
////////////////////	USB JTAG link	////////////////////////////
input  			TDI;					// CPLD -> FPGA (data in)
input  			TCK;					// CPLD -> FPGA (clk)
input  			TCS;					// CPLD -> FPGA (CS)
output 			TDO;					// FPGA -> CPLD (data out)
////////////////////////	VGA			////////////////////////////
output			VGA_CLK;   				//	VGA Clock
output			VGA_HS;					//	VGA H_SYNC
output			VGA_VS;					//	VGA V_SYNC
output			VGA_BLANK;				//	VGA BLANK
output			VGA_SYNC;				//	VGA SYNC
output	[9:0]	VGA_R;   				//	VGA Red[9:0]
output	[9:0]	VGA_G;	 				//	VGA Green[9:0]
output	[9:0]	VGA_B;   				//	VGA Blue[9:0]
////////////////	Ethernet Interface	////////////////////////////
inout	[15:0]	ENET_DATA;				//	DM9000A DATA bus 16Bits
output			ENET_CMD;				//	DM9000A Command/Data Select, 0 = Command, 1 = Data
output			ENET_CS_N;				//	DM9000A Chip Select
output			ENET_WR_N;				//	DM9000A Write
output			ENET_RD_N;				//	DM9000A Read
output			ENET_RST_N;				//	DM9000A Reset
input			ENET_INT;				//	DM9000A Interrupt
output			ENET_CLK;				//	DM9000A Clock 25 MHz
////////////////////	Audio CODEC		////////////////////////////
inout			AUD_ADCLRCK;			//	Audio CODEC ADC LR Clock
input			AUD_ADCDAT;				//	Audio CODEC ADC Data
inout			AUD_DACLRCK;			//	Audio CODEC DAC LR Clock
output			AUD_DACDAT;				//	Audio CODEC DAC Data
inout			AUD_BCLK;				//	Audio CODEC Bit-Stream Clock
output			AUD_XCK;				//	Audio CODEC Chip Clock
////////////////////	TV Devoder		////////////////////////////
input	[7:0]	TD_DATA;    			//	TV Decoder Data bus 8 bits
input			TD_HS;					//	TV Decoder H_SYNC
input			TD_VS;					//	TV Decoder V_SYNC
output			TD_RESET;				//	TV Decoder Reset
////////////////////////	GPIO	////////////////////////////////
inout	[35:0]	GPIO_0;					//	GPIO Connection 0
inout	[35:0]	GPIO_1;					//	GPIO Connection 1

//	Turn on all display
assign	HEX0		=	7'h00;
assign	HEX1		=	7'h00;
assign	HEX2		=	7'h00;
assign	HEX3		=	7'h00;
assign	HEX4		=	7'h00;
assign	HEX5		=	7'h00;
assign	HEX6		=	7'h00;
assign	HEX7		=	7'h00;
//assign	LEDG		=	9'h1FF;
assign	LEDR		=	18'h3FFFF;
assign	LCD_ON		=	1'b1;
assign	LCD_BLON	=	1'b1;

//	All inout port turn to tri-state
assign	DRAM_DQ		=	16'hzzzz;
assign	FL_DQ		=	8'hzz;
assign	SRAM_DQ		=	16'hzzzz;
assign	OTG_DATA	=	16'hzzzz;
assign	LCD_DATA	=	8'hzz;
assign	SD_DAT		=	1'bz;
assign	ENET_DATA	=	16'hzzzz;
assign	AUD_ADCLRCK	=	1'bz;
assign	AUD_DACLRCK	=	1'bz;
assign	AUD_BCLK	=	1'bz;
assign	GPIO_0		=	36'hzzzzzzzzz;
//assign	GPIO_1		=	36'hzzzzzzzzz;

wire	[7:0]	LCM_DATA;		//	LCM Data 8 Bits
wire			LCM_GRST;		//	LCM Global Reset	
wire			LCM_SHDB;		//	LCM Sleep Mode
wire			LCM_DCLK;		//	LCM Clcok
wire			LCM_HSYNC;		//	LCM HSYNC
wire			LCM_VSYNC;		//	LCM	VSYNC
wire			LCM_SCLK;		//	LCM I2C Clock
wire			LCM_SDAT;		//	LCM I2C Data
wire			LCM_SCEN;		//	LCM I2C Enable


assign	GPIO_0[18]	=	LCM_DATA[6];
assign	GPIO_0[19]	=	LCM_DATA[7];
assign	GPIO_0[20]	=	LCM_DATA[4];
assign	GPIO_0[21]	=	LCM_DATA[5];
assign	GPIO_0[22]	=	LCM_DATA[2];
assign	GPIO_0[23]	=	LCM_DATA[3];
assign	GPIO_0[24]	=	LCM_DATA[0];
assign	GPIO_0[25]	=	LCM_DATA[1];
assign	GPIO_0[26]	=	LCM_VSYNC;
assign	GPIO_0[28]	=	LCM_SCLK;
assign	GPIO_0[29]	=	LCM_DCLK;
assign	GPIO_0[30]	=	LCM_GRST;
assign	GPIO_0[31]	=	LCM_SHDB;
assign	GPIO_0[33]	=	LCM_SCEN;
assign	GPIO_0[34]	=	LCM_SDAT;
assign	GPIO_0[35]	=	LCM_HSYNC;

assign	LCM_GRST	=	KEY[0];
assign	TD_RESET	=	KEY[0];
assign	LCM_DCLK	=	~CLK_25;
assign	LCM_SHDB	=	1'b1;

wire			iCLK;
wire			iRST_N;
reg		[10:0]	H_Cont;
reg		[10:0]	V_Cont;
reg		[7:0]	Tmp_DATA;
reg				oVGA_H_SYNC;
reg				oVGA_V_SYNC;
reg				CLK_25;
wire	[1:0]	mSEL;

assign	iCLK		=	CLK_25;
assign	iRST_N		=	KEY[0];
assign	LCM_VSYNC	=	oVGA_V_SYNC;
assign	LCM_HSYNC	=	oVGA_H_SYNC;
//assign	LCM_DATA	=	(MOD_3==mSEL)	?	Tmp_DATA	:	8'h00	;
assign	LCM_DATA	=		(SW[1:0]==2'b00)	?	Tmp_DATA	:
							(SW[1:0]==2'b01)	?	((MOD_3==mSEL)	?	Tmp_DATA	:	8'h00)	:
							(SW[1:0]==2'b10)	?	8'h7F		:
													8'hFF		;
assign	mSEL		=	(V_Cont<94)					?	2'b01	:
						(V_Cont>=94	&& V_Cont<174)	?	2'b10	:
														2'b00	;

//	Horizontal Parameter	( Pixel )
parameter	H_SYNC_CYC	=	1;
parameter	H_SYNC_BACK	=	151;
parameter	H_SYNC_ACT	=	960;
parameter	H_SYNC_FRONT=	59;
parameter	H_SYNC_TOTAL=	1171;
//	Virtical Parameter		( Line )
parameter	V_SYNC_CYC	=	1;
parameter	V_SYNC_BACK	=	13;
parameter	V_SYNC_ACT	=	240;
parameter	V_SYNC_FRONT=	8;
parameter	V_SYNC_TOTAL=	262;

LCM_PLL 	u0	(	.inclk0(CLOCK_50),.c0(CLK_25));

reg		[1:0]	MOD_3;

always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		Tmp_DATA	<=	8'h00;
		MOD_3		<=	2'b00;	
	end
	else
	begin
		if(	H_Cont>H_SYNC_BACK && H_Cont<(H_SYNC_TOTAL-H_SYNC_FRONT) )
		begin
			if(MOD_3<2'b10)
			MOD_3	<=	MOD_3+1'b1;
			else
			MOD_3	<=	2'b00;
			Tmp_DATA<=	Tmp_DATA+1'b1;
		end
		else
		begin
			MOD_3	<=	2'b00;
			Tmp_DATA<=	8'h00;	
		end
	end
end

//	H_Sync Generator, Ref. 25.175 MHz Clock
always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		H_Cont		<=	0;
		oVGA_H_SYNC	<=	0;
	end
	else
	begin
		//	H_Sync Counter
		if( H_Cont < H_SYNC_TOTAL )
		H_Cont	<=	H_Cont+1;
		else
		H_Cont	<=	0;
		//	H_Sync Generator
		if( H_Cont < H_SYNC_CYC )
		oVGA_H_SYNC	<=	0;
		else
		oVGA_H_SYNC	<=	1;
	end
end

//	V_Sync Generator, Ref. H_Sync
always@(posedge iCLK or negedge iRST_N)
begin
	if(!iRST_N)
	begin
		V_Cont		<=	0;
		oVGA_V_SYNC	<=	0;
	end
	else
	begin
		//	When H_Sync Re-start
		if(H_Cont==0)
		begin
			//	V_Sync Counter
			if( V_Cont < V_SYNC_TOTAL )
			V_Cont	<=	V_Cont+1;
			else
			V_Cont	<=	0;
			//	V_Sync Generator
			if(	V_Cont < V_SYNC_CYC )
			oVGA_V_SYNC	<=	0;
			else
			oVGA_V_SYNC	<=	1;
		end
	end
end

I2S_LCM_Config 	u4	(	//	Host Side
						.iCLK(CLOCK_50),
						.iRST_N(KEY[0]),
						//	I2C Side
						.I2S_SCLK(LCM_SCLK),
						.I2S_SDAT(LCM_SDAT),
						.I2S_SCEN(LCM_SCEN)	);
endmodule