ila_pro_0.edn

verilog语言编写

                   (port (rename ADDRA_7_ "ADDRA<7>") (direction INPUT))
                   (port (rename ADDRA_8_ "ADDRA<8>") (direction INPUT))
                   (port (rename ADDRA_9_ "ADDRA<9>") (direction INPUT))
                   (port (rename ADDRA_10_ "ADDRA<10>") (direction INPUT))
                   (port (rename ADDRA_11_ "ADDRA<11>") (direction INPUT))
                   (port (rename ADDRA_12_ "ADDRA<12>") (direction INPUT))
                   (port (rename ADDRA_13_ "ADDRA<13>") (direction INPUT))
                   (port WEB (direction INPUT))
                   (port ENB (direction INPUT))
                   (port SSRB (direction INPUT))
                   (port CLKB (direction INPUT))
                   (port (rename DIB_0_ "DIB<0>") (direction INPUT))
                   (port (rename DIB_1_ "DIB<1>") (direction INPUT))
                   (port (rename DIB_2_ "DIB<2>") (direction INPUT))
                   (port (rename DIB_3_ "DIB<3>") (direction INPUT))
                   (port (rename DIB_4_ "DIB<4>") (direction INPUT))
                   (port (rename DIB_5_ "DIB<5>") (direction INPUT))
                   (port (rename DIB_6_ "DIB<6>") (direction INPUT))
                   (port (rename DIB_7_ "DIB<7>") (direction INPUT))
                   (port (rename DIB_8_ "DIB<8>") (direction INPUT))
                   (port (rename DIB_9_ "DIB<9>") (direction INPUT))
                   (port (rename DIB_10_ "DIB<10>") (direction INPUT))
                   (port (rename DIB_11_ "DIB<11>") (direction INPUT))
                   (port (rename DIB_12_ "DIB<12>") (direction INPUT))
                   (port (rename DIB_13_ "DIB<13>") (direction INPUT))
                   (port (rename DIB_14_ "DIB<14>") (direction INPUT))
                   (port (rename DIB_15_ "DIB<15>") (direction INPUT))
                   (port (rename DIB_16_ "DIB<16>") (direction INPUT))
                   (port (rename DIB_17_ "DIB<17>") (direction INPUT))
                   (port (rename DIB_18_ "DIB<18>") (direction INPUT))
                   (port (rename DIB_19_ "DIB<19>") (direction INPUT))
                   (port (rename DIB_20_ "DIB<20>") (direction INPUT))
                   (port (rename DIB_21_ "DIB<21>") (direction INPUT))
                   (port (rename DIB_22_ "DIB<22>") (direction INPUT))
                   (port (rename DIB_23_ "DIB<23>") (direction INPUT))
                   (port (rename DIB_24_ "DIB<24>") (direction INPUT))
                   (port (rename DIB_25_ "DIB<25>") (direction INPUT))
                   (port (rename DIB_26_ "DIB<26>") (direction INPUT))
                   (port (rename DIB_27_ "DIB<27>") (direction INPUT))
                   (port (rename DIB_28_ "DIB<28>") (direction INPUT))
                   (port (rename DIB_29_ "DIB<29>") (direction INPUT))
                   (port (rename DIB_30_ "DIB<30>") (direction INPUT))
                   (port (rename DIB_31_ "DIB<31>") (direction INPUT))
                   (port (rename DOB_0_ "DOB<0>") (direction OUTPUT))
                   (port (rename DOB_1_ "DOB<1>") (direction OUTPUT))
                   (port (rename DOB_2_ "DOB<2>") (direction OUTPUT))
                   (port (rename DOB_3_ "DOB<3>") (direction OUTPUT))
                   (port (rename DOB_4_ "DOB<4>") (direction OUTPUT))
                   (port (rename DOB_5_ "DOB<5>") (direction OUTPUT))
                   (port (rename DOB_6_ "DOB<6>") (direction OUTPUT))
                   (port (rename DOB_7_ "DOB<7>") (direction OUTPUT))
                   (port (rename DOB_8_ "DOB<8>") (direction OUTPUT))
                   (port (rename DOB_9_ "DOB<9>") (direction OUTPUT))
                   (port (rename DOB_10_ "DOB<10>") (direction OUTPUT))
                   (port (rename DOB_11_ "DOB<11>") (direction OUTPUT))
                   (port (rename DOB_12_ "DOB<12>") (direction OUTPUT))
                   (port (rename DOB_13_ "DOB<13>") (direction OUTPUT))
                   (port (rename DOB_14_ "DOB<14>") (direction OUTPUT))
                   (port (rename DOB_15_ "DOB<15>") (direction OUTPUT))
                   (port (rename DOB_16_ "DOB<16>") (direction OUTPUT))
                   (port (rename DOB_17_ "DOB<17>") (direction OUTPUT))
                   (port (rename DOB_18_ "DOB<18>") (direction OUTPUT))
                   (port (rename DOB_19_ "DOB<19>") (direction OUTPUT))
                   (port (rename DOB_20_ "DOB<20>") (direction OUTPUT))
                   (port (rename DOB_21_ "DOB<21>") (direction OUTPUT))
                   (port (rename DOB_22_ "DOB<22>") (direction OUTPUT))
                   (port (rename DOB_23_ "DOB<23>") (direction OUTPUT))
                   (port (rename DOB_24_ "DOB<24>") (direction OUTPUT))
                   (port (rename DOB_25_ "DOB<25>") (direction OUTPUT))
                   (port (rename DOB_26_ "DOB<26>") (direction OUTPUT))
                   (port (rename DOB_27_ "DOB<27>") (direction OUTPUT))
                   (port (rename DOB_28_ "DOB<28>") (direction OUTPUT))
                   (port (rename DOB_29_ "DOB<29>") (direction OUTPUT))
                   (port (rename DOB_30_ "DOB<30>") (direction OUTPUT))
                   (port (rename DOB_31_ "DOB<31>") (direction OUTPUT))
                   (port (rename ADDRB_0_ "ADDRB<0>") (direction INPUT))
                   (port (rename ADDRB_1_ "ADDRB<1>") (direction INPUT))
                   (port (rename ADDRB_2_ "ADDRB<2>") (direction INPUT))
                   (port (rename ADDRB_3_ "ADDRB<3>") (direction INPUT))
                   (port (rename ADDRB_4_ "ADDRB<4>") (direction INPUT))
                   (port (rename ADDRB_5_ "ADDRB<5>") (direction INPUT))
                   (port (rename ADDRB_6_ "ADDRB<6>") (direction INPUT))
                   (port (rename ADDRB_7_ "ADDRB<7>") (direction INPUT))
                   (port (rename ADDRB_8_ "ADDRB<8>") (direction INPUT))
                   (port (rename DIPB_0_ "DIPB<0>") (direction INPUT))
                   (port (rename DIPB_1_ "DIPB<1>") (direction INPUT))
                   (port (rename DIPB_2_ "DIPB<2>") (direction INPUT))
                   (port (rename DIPB_3_ "DIPB<3>") (direction INPUT))
                   (port (rename DOPB_0_ "DOPB<0>") (direction OUTPUT))
                   (port (rename DOPB_1_ "DOPB<1>") (direction OUTPUT))
                   (port (rename DOPB_2_ "DOPB<2>") (direction OUTPUT))
                   (port (rename DOPB_3_ "DOPB<3>") (direction OUTPUT))
               )
           )
       )
       (cell SRL16 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port CLK (direction INPUT))
                   (port A0 (direction INPUT))
                   (port A1 (direction INPUT))
                   (port A2 (direction INPUT))
                   (port A3 (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell SRL16E (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLK (direction INPUT))
                   (port A0 (direction INPUT))
                   (port A1 (direction INPUT))
                   (port A2 (direction INPUT))
                   (port A3 (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell SRLC16E (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLK (direction INPUT))
                   (port A0 (direction INPUT))
                   (port A1 (direction INPUT))
                   (port A2 (direction INPUT))
                   (port A3 (direction INPUT))
                   (port Q (direction OUTPUT))
                   (port Q15 (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell ila_pro_0
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename clk "clk") (direction INPUT))
   (port ( rename trig0_5_ "trig0<5>") (direction INPUT))
   (port ( rename trig0_4_ "trig0<4>") (direction INPUT))
   (port ( rename trig0_3_ "trig0<3>") (direction INPUT))
   (port ( rename trig0_2_ "trig0<2>") (direction INPUT))
   (port ( rename trig0_1_ "trig0<1>") (direction INPUT))
   (port ( rename trig0_0_ "trig0<0>") (direction INPUT))
   (port ( rename control_35_ "control<35>") (direction INOUT))
   (port ( rename control_34_ "control<34>") (direction INOUT))
   (port ( rename control_33_ "control<33>") (direction INOUT))
   (port ( rename control_32_ "control<32>") (direction INOUT))
   (port ( rename control_31_ "control<31>") (direction INOUT))
   (port ( rename control_30_ "control<30>") (direction INOUT))
   (port ( rename control_29_ "control<29>") (direction INOUT))
   (port ( rename control_28_ "control<28>") (direction INOUT))
   (port ( rename control_27_ "control<27>") (direction INOUT))
   (port ( rename control_26_ "control<26>") (direction INOUT))
   (port ( rename control_25_ "control<25>") (direction INOUT))
   (port ( rename control_24_ "control<24>") (direction INOUT))
   (port ( rename control_23_ "control<23>") (direction INOUT))
   (port ( rename control_22_ "control<22>") (direction INOUT))
   (port ( rename control_21_ "control<21>") (direction INOUT))
   (port ( rename control_20_ "control<20>") (direction INOUT))
   (port ( rename control_19_ "control<19>") (direction INOUT))
   (port ( rename control_18_ "control<18>") (direction INOUT))
   (port ( rename control_17_ "control<17>") (direction INOUT))
   (port ( rename control_16_ "control<16>") (direction INOUT))
   (port ( rename control_15_ "control<15>") (direction INOUT))
   (port ( rename control_14_ "control<14>") (direction INOUT))
   (port ( rename control_13_ "control<13>") (direction INOUT))
   (port ( rename control_12_ "control<12>") (direction INOUT))
   (port ( rename control_11_ "control<11>") (direction INOUT))
   (port ( rename control_10_ "control<10>") (direction INOUT))
   (port ( rename control_9_ "control<9>") (direction INOUT))
   (port ( rename control_8_ "control<8>") (direction INOUT))
   (port ( rename control_7_ "control<7>") (direction INOUT))
   (port ( rename control_6_ "control<6>") (direction INOUT))
   (port ( rename control_5_ "control<5>") (direction INOUT))
   (port ( rename control_4_ "control<4>") (direction INOUT))
   (port ( rename control_3_ "control<3>") (direction INOUT))
   (port ( rename control_2_ "control<2>") (direction INOUT))
   (port ( rename control_1_ "control<1>") (direction INOUT))
   (port ( rename control_0_ "control<0>") (direction INOUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance (rename ila_pro_0_i_tq0_g_tw_0_u_tq "ila_pro_0/i_tq0/g_tw/0/u_tq")
      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
   )
   (instance (rename ila_pro_0_i_tq0_g_tw_1_u_tq "ila_pro_0/i_tq0/g_tw/1/u_tq")
      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
   )
   (instance (rename ila_pro_0_i_tq0_g_tw_2_u_tq "ila_pro_0/i_tq0/g_tw/2/u_tq")
      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
   )
   (instance (rename ila_pro_0_i_tq0_g_tw_3_u_tq "ila_pro_0/i_tq0/g_tw/3/u_tq")
      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
   )
   (instance (rename ila_pro_0_i_tq0_g_tw_4_u_tq "ila_pro_0/i_tq0/g_tw/4/u_tq")
      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
   )
   (instance (rename ila_pro_0_i_tq0_g_tw_5_u_tq "ila_pro_0/i_tq0/g_tw/5/u_tq")
      (viewRef view_1 (cellRef FDP (libraryRef xilinxun)))
   )
   (instance (rename ila_pro_0_i_no_d_u_ila_i_dq_u_dqq_dly_9_dly_9_gen_0_i_srlt_ne_0_dly9 "ila_pro_0/i_no_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/dly9")
      (viewRef view_1 (cellRef SRL16 (libraryRef xilinxun)))
      (property INIT (string "0000"))
   )
   (instance (rename ila_pro_0_i_no_d_u_ila_i_dq_u_dqq_dly_9_dly_9_gen_0_i_srlt_ne_0_ff "ila_pro_0/i_no_d/u_ila/i_dq/u_dqq/dly_9/dly_9_gen/0/i_srlt_ne_0/ff")