trafficlight.map.rpt

Verilog hdl开发的交通灯完整实例

; countersel.v                     ; yes             ; F:/dolphin/trafficlight/countersel.v                                ;
; counter05.v                      ; yes             ; F:/dolphin/trafficlight/counter05.v                                 ;
; dispdecoder.v                    ; yes             ; F:/dolphin/trafficlight/dispdecoder.v                               ;
; dispmux.v                        ; yes             ; F:/dolphin/trafficlight/dispmux.v                                   ;
; datamux.v                        ; yes             ; F:/dolphin/trafficlight/datamux.v                                   ;
; dispselect.v                     ; yes             ; F:/dolphin/trafficlight/dispselect.v                                ;
; lpm_counter.tdf                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf         ;
; lpm_constant.inc                 ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_constant.inc        ;
; lpm_decode.inc                   ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_decode.inc          ;
; lpm_add_sub.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc         ;
; cmpconst.inc                     ; yes             ; c:/altera/quartus42/libraries/megafunctions/cmpconst.inc            ;
; lpm_compare.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_compare.inc         ;
; lpm_counter.inc                  ; yes             ; c:/altera/quartus42/libraries/megafunctions/lpm_counter.inc         ;
; dffeea.inc                       ; yes             ; c:/altera/quartus42/libraries/megafunctions/dffeea.inc              ;
; alt_synch_counter.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc   ;
; alt_synch_counter_f.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc            ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc   ;
; alt_counter_stratix.inc          ; yes             ; c:/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc                    ; yes             ; c:/altera/quartus42/libraries/megafunctions/aglobal42.inc           ;
; db/cntr_0b7.tdf                  ; yes             ; F:/dolphin/trafficlight/db/cntr_0b7.tdf                             ;
; db/cntr_cv7.tdf                  ; yes             ; F:/dolphin/trafficlight/db/cntr_cv7.tdf                             ;
; db/cntr_hc7.tdf                  ; yes             ; F:/dolphin/trafficlight/db/cntr_hc7.tdf                             ;
+----------------------------------+-----------------+---------------------------------------------------------------------+


+-------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                 ;
+-----------------------------------+-------------------------+
; Resource                          ; Usage                   ;
+-----------------------------------+-------------------------+
; Logic cells                       ; 154                     ;
; Total combinational functions     ; 149                     ;
; Total 4-input functions           ; 51                      ;
; Total 3-input functions           ; 8                       ;
; Total 2-input functions           ; 7                       ;
; Total 1-input functions           ; 83                      ;
; Total 0-input functions           ; 0                       ;
; Combinational cells for routing   ; 0                       ;
; Total registers                   ; 83                      ;
; Total logic cells in carry chains ; 83                      ;
; I/O pins                          ; 19                      ;
; Maximum fan-out node              ; fdiv1khz:inst12|clk_out ;
; Maximum fan-out                   ; 34                      ;
; Total fan-out                     ; 586                     ;
; Average fan-out                   ; 3.39                    ;
+-----------------------------------+-------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
    Info: Processing started: Sun May 28 11:09:56 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off trafficlight -c trafficlight
Info: Found 1 design units, including 1 entities, in source file trafficlight.bdf
    Info: Found entity 1: trafficlight
Info: Found 0 design units, including 0 entities, in source file trafficlight.v
Info: Using design file control.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: control
Info: Using design file scan.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: scan
Info: Using design file counter55.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: counter55
Warning: Verilog HDL assignment warning at counter55.v(37): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at counter55.v(42): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at counter55.v(63): truncated value with size 8 to match size of target (4)
Info: Using design file fdiv1hz.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fdiv1hz
Info: Using design file fdiv1khz.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fdiv1khz
Info: Using design file countersel.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: countersel
Info: Using design file counter05.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: counter05
Warning: Verilog HDL assignment warning at counter05.v(32): truncated value with size 5 to match size of target (4)
Info: Using design file dispdecoder.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispdecoder
Info: Using design file dispmux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispmux
Info: Using design file datamux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: datamux
Info: Using design file dispselect.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: dispselect
Warning: Reduced register "counter05:inst1|CData1[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "counter05:inst1|CData1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "counter05:inst1|CData1[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "counter05:inst1|CData1[0]" with stuck data_in port to stuck value GND
Info: Inferred 5 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter55:inst2|CData0[0]~20"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter05:inst1|CData0[0]~15"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "counter55:inst2|CData1[0]~25"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv1khz:inst12|cnt[0]~64"
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=32) from the following logic: "fdiv1hz:inst11|cnt[0]~64"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file db/cntr_0b7.tdf
    Info: Found entity 1: cntr_0b7
Info: Found 1 design units, including 1 entities, in source file db/cntr_cv7.tdf
    Info: Found entity 1: cntr_cv7
Info: Found 1 design units, including 1 entities, in source file db/cntr_hc7.tdf
    Info: Found entity 1: cntr_hc7
Info: Duplicate registers merged to single register
    Info: Duplicate register "dispselect:inst9|D_OUT[1]" merged to single register "dispselect:inst9|D_OUT[0]", power-up level changed
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "SEG_Data[0]" stuck at GND
Info: Implemented 173 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 16 output pins
    Info: Implemented 154 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Sun May 28 11:10:03 2006
    Info: Elapsed time: 00:00:08