prev_cmp_qiangdaqi.map.qmsg

抢答器。可以直接用QUARTUS2运行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Jan 12 13:29:35 2008 " "Info: Processing started: Sat Jan 12 13:29:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off qiangdaqi -c qiangdaqi" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "qiangdaqi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file qiangdaqi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 qiangdaqi-rtl " "Info: Found design unit 1: qiangdaqi-rtl" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 qiangdaqi " "Info: Found entity 1: qiangdaqi" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "first.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file first.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 first-rtl " "Info: Found design unit 1: first-rtl" {  } { { "first.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/first.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 first " "Info: Found entity 1: first" {  } { { "first.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/first.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "qiangdaqi " "Info: Elaborating entity \"qiangdaqi\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "mm1 qiangdaqi.vhd(14) " "Warning (10036): Verilog HDL or VHDL warning at qiangdaqi.vhd(14): object \"mm1\" assigned a value but never read" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 14 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "mm2 qiangdaqi.vhd(14) " "Warning (10036): Verilog HDL or VHDL warning at qiangdaqi.vhd(14): object \"mm2\" assigned a value but never read" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 14 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "mm3 qiangdaqi.vhd(14) " "Warning (10036): Verilog HDL or VHDL warning at qiangdaqi.vhd(14): object \"mm3\" assigned a value but never read" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 14 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "m1 qiangdaqi.vhd(6) " "Warning (10034): Output port \"m1\" at qiangdaqi.vhd(6) has no driver" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "m2 qiangdaqi.vhd(6) " "Warning (10034): Output port \"m2\" at qiangdaqi.vhd(6) has no driver" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "m3 qiangdaqi.vhd(6) " "Warning (10034): Output port \"m3\" at qiangdaqi.vhd(6) has no driver" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 6 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "first first:u1 " "Info: Elaborating entity \"first\" for hierarchy \"first:u1\"" {  } { { "qiangdaqi.vhd" "u1" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 20 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "m1 GND " "Warning: Pin \"m1\" stuck at GND" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m2 GND " "Warning: Pin \"m2\" stuck at GND" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "m3 GND " "Warning: Pin \"m3\" stuck at GND" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 6 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "a " "Warning: No output dependent on input pin \"a\"" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "b " "Warning: No output dependent on input pin \"b\"" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0} { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "c " "Warning: No output dependent on input pin \"c\"" {  } { { "qiangdaqi.vhd" "" { Text "F:/school/EDA/王志娟EDA/qiangdaqi/qiangdaqi.vhd" 5 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "6 " "Info: Implemented 6 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "174 " "Info: Allocated 174 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 12 13:29:38 2008 " "Info: Processing ended: Sat Jan 12 13:29:38 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}