qiangdaqi.vhd.bak

抢答器。可以直接用QUARTUS2运行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY qiangdaqi IS
PORT(a,b,c	 :IN STD_LOGIC;
	 m1,m2,m3:OUT STD_LOGIC);
END;

ARCHITECTURE rtl OF qiangdaqi IS
COMPONENT first 
	PORT(a,b,c:IN STD_LOGIC;
		     m:OUT STD_LOGIC);
END COMPONENT;
SIGNAL aa,bb,cc,mm1,mm2,mm3: STD_LOGIC;
BEGIN
		aa<=not a;
		bb<=not b;
		cc<=not c;
		
		u1:first port map(a,bb,cc,mm1);
		u2:first port map(aa,b,cc,mm2);
		u3:first port map(aa,bb,c,mm3);
END;