qiangdaqi.tan.rpt

抢答器。可以直接用QUARTUS2运行

Classic Timing Analyzer report for qiangdaqi
Sat Jan 12 13:34:27 2008
Quartus II Version 7.1 Build 156 04/30/2007 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. tpd
  5. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                               ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd               ; N/A   ; None          ; 7.443 ns    ; b    ; m2 ; --         ; --       ; 0            ;
; Total number of failed paths ;       ;               ;             ;      ;    ;            ;          ; 0            ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 7.443 ns        ; b    ; m2 ;
; N/A   ; None              ; 7.438 ns        ; b    ; m3 ;
; N/A   ; None              ; 7.433 ns        ; b    ; m1 ;
; N/A   ; None              ; 7.209 ns        ; a    ; m2 ;
; N/A   ; None              ; 7.199 ns        ; a    ; m1 ;
; N/A   ; None              ; 7.134 ns        ; c    ; m2 ;
; N/A   ; None              ; 7.123 ns        ; c    ; m1 ;
; N/A   ; None              ; 7.114 ns        ; c    ; m3 ;
; N/A   ; None              ; 6.930 ns        ; a    ; m3 ;
+-------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Sat Jan 12 13:34:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qiangdaqi -c qiangdaqi --timing_analysis_only
Info: Longest tpd from source pin "b" to destination pin "m2" is 7.443 ns
    Info: 1: + IC(0.000 ns) + CELL(0.807 ns) = 0.807 ns; Loc. = PIN_R15; Fanout = 3; PIN Node = 'b'
    Info: 2: + IC(3.799 ns) + CELL(0.346 ns) = 4.952 ns; Loc. = LCCOMB_X1_Y2_N0; Fanout = 1; COMB Node = 'first:u2|m'
    Info: 3: + IC(0.327 ns) + CELL(2.164 ns) = 7.443 ns; Loc. = PIN_W22; Fanout = 0; PIN Node = 'm2'
    Info: Total cell delay = 3.317 ns ( 44.57 % )
    Info: Total interconnect delay = 4.126 ns ( 55.43 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Allocated 137 megabytes of memory during processing
    Info: Processing ended: Sat Jan 12 13:34:27 2008
    Info: Elapsed time: 00:00:01