div_js.tan.rpt

技术分频器。把时钟分为奇数个

; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[0]~DUPLICATE ; count1[3]           ; clk        ; clk      ; None                        ; None                      ; 0.750 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[1]           ; tmp2                ; clk        ; clk      ; None                        ; None                      ; 0.730 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[2]           ; count1[3]           ; clk        ; clk      ; None                        ; None                      ; 0.728 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[1]           ; count2[2]           ; clk        ; clk      ; None                        ; None                      ; 0.727 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[0]           ; count2[3]           ; clk        ; clk      ; None                        ; None                      ; 0.650 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[2]           ; tmp1                ; clk        ; clk      ; None                        ; None                      ; 0.636 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[0]           ; count1[2]           ; clk        ; clk      ; None                        ; None                      ; 0.635 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[0]           ; count2[1]           ; clk        ; clk      ; None                        ; None                      ; 0.575 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[1]           ; count1[3]           ; clk        ; clk      ; None                        ; None                      ; 0.509 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; tmp2                ; tmp2                ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[2]           ; count2[2]           ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[0]           ; count2[0]           ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[1]           ; count2[1]           ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[3]           ; count2[3]           ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; tmp1                ; tmp1                ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[1]           ; count1[1]           ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[2]           ; count1[2]           ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[3]           ; count1[3]           ; clk        ; clk      ; None                        ; None                      ; 0.488 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[3]           ; count1[2]           ; clk        ; clk      ; None                        ; None                      ; 0.430 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[3]           ; count2[2]           ; clk        ; clk      ; None                        ; None                      ; 0.428 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[3]           ; tmp2                ; clk        ; clk      ; None                        ; None                      ; 0.423 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[0]           ; count1[1]           ; clk        ; clk      ; None                        ; None                      ; 0.422 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count2[1]           ; count2[3]           ; clk        ; clk      ; None                        ; None                      ; 0.421 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[3]           ; tmp1                ; clk        ; clk      ; None                        ; None                      ; 0.421 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[0]~DUPLICATE ; count1[0]~DUPLICATE ; clk        ; clk      ; None                        ; None                      ; 0.396 ns                ;
; N/A   ; Restricted to 500.00 MHz ( period = 2.000 ns ) ; count1[0]           ; count1[0]           ; clk        ; clk      ; None                        ; None                      ; 0.396 ns                ;
+-------+------------------------------------------------+---------------------+---------------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To     ; From Clock ;
+-------+--------------+------------+------+--------+------------+
; N/A   ; None         ; 5.716 ns   ; tmp1 ; clkout ; clk        ;
; N/A   ; None         ; 5.584 ns   ; tmp2 ; clkout ; clk        ;
+-------+--------------+------------+------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Sat Jan 12 13:17:28 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off div_js -c div_js --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "count1[1]" and destination register "tmp1"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.807 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y26_N7; Fanout = 4; REG Node = 'count1[1]'
            Info: 2: + IC(0.286 ns) + CELL(0.366 ns) = 0.652 ns; Loc. = LCCOMB_X25_Y26_N22; Fanout = 1; COMB Node = 'tmp1~33'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.807 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'
            Info: Total cell delay = 0.521 ns ( 64.56 % )
            Info: Total interconnect delay = 0.286 ns ( 35.44 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.497 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'
                Info: Total cell delay = 1.472 ns ( 58.95 % )
                Info: Total interconnect delay = 1.025 ns ( 41.05 % )
            Info: - Longest clock path from clock "clk" to source register is 2.497 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X25_Y26_N7; Fanout = 4; REG Node = 'count1[1]'
                Info: Total cell delay = 1.472 ns ( 58.95 % )
                Info: Total interconnect delay = 1.025 ns ( 41.05 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tco from clock "clk" to destination pin "clkout" through register "tmp1" is 5.716 ns
    Info: + Longest clock path from clock "clk" to source register is 2.497 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 11; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.682 ns) + CELL(0.618 ns) = 2.497 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'
        Info: Total cell delay = 1.472 ns ( 58.95 % )
        Info: Total interconnect delay = 1.025 ns ( 41.05 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 3.125 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y26_N23; Fanout = 2; REG Node = 'tmp1'
        Info: 2: + IC(0.264 ns) + CELL(0.346 ns) = 0.610 ns; Loc. = LCCOMB_X25_Y26_N30; Fanout = 1; COMB Node = 'clkout~0'
        Info: 3: + IC(0.479 ns) + CELL(2.036 ns) = 3.125 ns; Loc. = PIN_D10; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 2.382 ns ( 76.22 % )
        Info: Total interconnect delay = 0.743 ns ( 23.78 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 137 megabytes of memory during processing
    Info: Processing ended: Sat Jan 12 13:17:29 2008
    Info: Elapsed time: 00:00:01