clkdiv_2p5.vhd

来自「2.5分频器。算是小数分频的一个例子。我们以前做实验的时候用来写实验报告滴~还有」· VHDL 代码 · 共 36 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ClkDiv_2p5 IS
PORT(clk:IN STD_LOGIC;
	 clkdiv2p5:OUT STD_LOGIC);
END ENTITY ClkDiv_2p5;
ARCHITECTURE rtl OF ClkDiv_2p5 IS
CONSTANT md			:STD_LOGIC_VECTOR(1 DOWNTO 0):="10";
SIGNAL counter		:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL tmpclk		:STD_LOGIC;
SIGNAL clkdiv5		:STD_LOGIC;
SIGNAL tmpdiv2p5	:STD_LOGIC;
BEGIN 
	p1:PROCESS(tmpclk)
	BEGIN
		IF(tmpclk'event AND tmpclk='1')THEN
			IF(counter="00")THEN
				counter<=md;
				tmpdiv2p5<='1';
			ELSE 
				counter<=counter-1;tmpdiv2p5<='0';
			END IF;
		END IF;
	END PROCESS p1;
	p2:PROCESS(tmpdiv2p5)
	BEGIN 
		IF(tmpdiv2p5'event AND tmpdiv2p5='1')THEN
			clkdiv5<=NOT clkdiv5;
		END IF;
	END PROCESS p2;
	tmpclk<=clk XOR clkdiv5;
	clkdiv2p5<=tmpdiv2p5;
END rtl;