clkdiv_2p5.tan.qmsg

2.5分频器。算是小数分频的一个例子。我们以前做实验的时候用来写实验报告滴~还有好多呢

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clkdiv5 " "Info: Detected ripple clock \"clkdiv5\" as buffer" {  } { { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 13 -1 0 } } { "g:/qartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/qartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clkdiv5" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "tmpclk " "Info: Detected gated clock \"tmpclk\" as buffer" {  } { { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 12 -1 0 } } { "g:/qartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/qartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "tmpclk" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "tmpdiv2p5 " "Info: Detected ripple clock \"tmpdiv2p5\" as buffer" {  } { { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } } { "g:/qartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "g:/qartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "tmpdiv2p5" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register counter\[0\] tmpdiv2p5 125.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 125.0 MHz between source register \"counter\[0\]\" and destination register \"tmpdiv2p5\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.300 ns + Longest register register " "Info: + Longest register to register delay is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LC3_F2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F2; Fanout = 3; REG Node = 'counter\[0\]'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[0] } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.700 ns) 2.300 ns tmpdiv2p5 2 REG LC2_F2 2 " "Info: 2: + IC(0.600 ns) + CELL(1.700 ns) = 2.300 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { counter[0] tmpdiv2p5 } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns ( 73.91 % ) " "Info: Total cell delay = 1.700 ns ( 73.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 26.09 % ) " "Info: Total interconnect delay = 0.600 ns ( 26.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { counter[0] tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { counter[0] tmpdiv2p5 } { 0.000ns 0.600ns } { 0.000ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 10.500 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_210 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_210; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.800 ns) 6.100 ns tmpclk 2 COMB LC1_F2 3 " "Info: 2: + IC(1.500 ns) + CELL(1.800 ns) = 6.100 ns; Loc. = LC1_F2; Fanout = 3; COMB Node = 'tmpclk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { clk tmpclk } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.500 ns tmpdiv2p5 3 REG LC2_F2 2 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { tmpclk tmpdiv2p5 } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 43.81 % ) " "Info: Total cell delay = 4.600 ns ( 43.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.900 ns ( 56.19 % ) " "Info: Total interconnect delay = 5.900 ns ( 56.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk tmpdiv2p5 } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.500 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_210 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_210; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.800 ns) 6.100 ns tmpclk 2 COMB LC1_F2 3 " "Info: 2: + IC(1.500 ns) + CELL(1.800 ns) = 6.100 ns; Loc. = LC1_F2; Fanout = 3; COMB Node = 'tmpclk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { clk tmpclk } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.500 ns counter\[0\] 3 REG LC3_F2 3 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC3_F2; Fanout = 3; REG Node = 'counter\[0\]'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { tmpclk counter[0] } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 43.81 % ) " "Info: Total cell delay = 4.600 ns ( 43.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.900 ns ( 56.19 % ) " "Info: Total interconnect delay = 5.900 ns ( 56.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk counter[0] } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk counter[0] } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk tmpdiv2p5 } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk counter[0] } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk counter[0] } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.300 ns" { counter[0] tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "2.300 ns" { counter[0] tmpdiv2p5 } { 0.000ns 0.600ns } { 0.000ns 1.700ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk tmpdiv2p5 } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk counter[0] } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk counter[0] } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { tmpdiv2p5 } {  } {  } "" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clkdiv2p5 tmpdiv2p5 17.600 ns register " "Info: tco from clock \"clk\" to destination pin \"clkdiv2p5\" through register \"tmpdiv2p5\" is 17.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 10.500 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_210 1 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_210; Fanout = 1; CLK Node = 'clk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(1.800 ns) 6.100 ns tmpclk 2 COMB LC1_F2 3 " "Info: 2: + IC(1.500 ns) + CELL(1.800 ns) = 6.100 ns; Loc. = LC1_F2; Fanout = 3; COMB Node = 'tmpclk'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { clk tmpclk } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(0.000 ns) 10.500 ns tmpdiv2p5 3 REG LC2_F2 2 " "Info: 3: + IC(4.400 ns) + CELL(0.000 ns) = 10.500 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { tmpclk tmpdiv2p5 } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns ( 43.81 % ) " "Info: Total cell delay = 4.600 ns ( 43.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.900 ns ( 56.19 % ) " "Info: Total interconnect delay = 5.900 ns ( 56.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk tmpdiv2p5 } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register pin " "Info: + Longest register to pin delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns tmpdiv2p5 1 REG LC2_F2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_F2; Fanout = 2; REG Node = 'tmpdiv2p5'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { tmpdiv2p5 } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.900 ns) + CELL(5.100 ns) 6.000 ns clkdiv2p5 2 PIN PIN_119 0 " "Info: 2: + IC(0.900 ns) + CELL(5.100 ns) = 6.000 ns; Loc. = PIN_119; Fanout = 0; PIN Node = 'clkdiv2p5'" {  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { tmpdiv2p5 clkdiv2p5 } "NODE_NAME" } } { "ClkDiv_2p5.vhd" "" { Text "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.100 ns ( 85.00 % ) " "Info: Total cell delay = 5.100 ns ( 85.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.900 ns ( 15.00 % ) " "Info: Total interconnect delay = 0.900 ns ( 15.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { tmpdiv2p5 clkdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { tmpdiv2p5 clkdiv2p5 } { 0.000ns 0.900ns } { 0.000ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "10.500 ns" { clk tmpclk tmpdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "10.500 ns" { clk clk~out tmpclk tmpdiv2p5 } { 0.000ns 0.000ns 1.500ns 4.400ns } { 0.000ns 2.800ns 1.800ns 0.000ns } "" } } { "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "g:/qartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.000 ns" { tmpdiv2p5 clkdiv2p5 } "NODE_NAME" } } { "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "g:/qartus2/quartus/bin/Technology_Viewer.qrui" "6.000 ns" { tmpdiv2p5 clkdiv2p5 } { 0.000ns 0.900ns } { 0.000ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "106 " "Info: Allocated 106 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 03 11:48:54 2007 " "Info: Processing ended: Mon Dec 03 11:48:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}