clkdiv_2p5.sim.rpt

2.5分频器。算是小数分频的一个例子。我们以前做实验的时候用来写实验报告滴~还有好多呢

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                          ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+
; Node Name                                                                       ; Output Port Name                                                                ; Output Port Type ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+
; |ClkDiv_2p5|counter[0]                                                          ; |ClkDiv_2p5|counter[0]                                                          ; regout           ;
; |ClkDiv_2p5|counter~0                                                           ; |ClkDiv_2p5|counter~0                                                           ; out              ;
; |ClkDiv_2p5|counter~1                                                           ; |ClkDiv_2p5|counter~1                                                           ; out              ;
; |ClkDiv_2p5|tmpdiv2p5                                                           ; |ClkDiv_2p5|tmpdiv2p5                                                           ; regout           ;
; |ClkDiv_2p5|tmpclk                                                              ; |ClkDiv_2p5|tmpclk                                                              ; out0             ;
; |ClkDiv_2p5|counter[1]                                                          ; |ClkDiv_2p5|counter[1]                                                          ; regout           ;
; |ClkDiv_2p5|clk                                                                 ; |ClkDiv_2p5|clk                                                                 ; out              ;
; |ClkDiv_2p5|clkdiv2p5                                                           ; |ClkDiv_2p5|clkdiv2p5                                                           ; pin_out          ;
; |ClkDiv_2p5|Equal0~3                                                            ; |ClkDiv_2p5|Equal0~3                                                            ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|result_node[1]                                     ; |ClkDiv_2p5|lpm_add_sub:Add0|result_node[1]                                     ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|result_node[2]                                     ; |ClkDiv_2p5|lpm_add_sub:Add0|result_node[2]                                     ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~1                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]~1                  ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~2                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]~2                  ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[2]                    ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[1]                    ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~4                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~4                                  ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~7                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~7                                  ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~8                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~8                                  ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~9                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~9                                  ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~10                                 ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~10                                 ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~11                                 ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~11                                 ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; sout             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1]      ; cout             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; sout             ;
+---------------------------------------------------------------------------------+---------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                        ;
+---------------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; Node Name                                                                       ; Output Port Name                                                           ; Output Port Type ;
+---------------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0                      ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0                 ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]                        ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]                   ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~0                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~0                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~1                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~1                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~2                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~2                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~3                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~3                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1                      ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1                 ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]                        ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]                   ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[1]                        ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[1]                   ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~5                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~5                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~6                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~6                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout             ;
+---------------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                                                                                        ;
+---------------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; Node Name                                                                       ; Output Port Name                                                           ; Output Port Type ;
+---------------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0                      ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]~0                 ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]                        ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[0]                   ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]~0             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]                    ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|unreg_res_node[0]               ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~0                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~0                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~1                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~1                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~2                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~2                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~3                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~3                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1                      ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]~1                 ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]                        ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[2]                   ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[1]                        ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|datab_node[1]                   ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~5                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~5                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~6                                  ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|_~6                             ; out0             ;
; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[0] ; |ClkDiv_2p5|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout             ;
+---------------------------------------------------------------------------------+----------------------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition
    Info: Processing started: Mon Dec 03 11:55:27 2007
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off ClkDiv_2p5 -c ClkDiv_2p5
Info: Using vector source file "F:/school/EDA/王志娟EDA/ClkDiv_2p5/ClkDiv_2p5.vwf"
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      63.16 %
Info: Number of transitions in simulation is 2798
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Allocated 91 megabytes of memory during processing
    Info: Processing ended: Mon Dec 03 11:55:28 2007
    Info: Elapsed time: 00:00:01