opb_epp.vhd

MicroBlaze 外设,opb_epp利用pc并可与MicroBlaze进行通信

	  wb_stb_I, wb_we_I: in std_logic; 
	  -- wb_cyc_I: in std_logic; -- signal is ignored
	  -- wb_rst_I: in std_logic; -- the WISHBONE interface need not be reseted
	  wb_ack_O: buffer std_logic); 
  end component;
	
-- Find LA Address Width
function log2(arg: integer) return integer is
    variable ret: integer:= -1;
  begin
	for i in 0 to 4 loop
	  if 2**i = arg then ret:= i; end if;
	end loop;
    return ret;
  end log2;
	
  signal arst: std_logic; -- asynchronous global reset
  constant la_awidth: integer:= 1 + c_la_mwidth + log2(c_la_dwidth/8);
  constant gnd32: std_logic_vector(31 downto 0):= (others=>'0');
  
  type epp_sel_type is (s_w2o, s_rst, s_la); -- epp which device selects 
    -- (w2o -wishbone2 OPB, s_rst- reset register, s_la<= select Logic analyser)
  signal epp_sel: epp_sel_type;
  
  signal epp_adr: std_logic_vector(31 downto 0); -- epp address
  signal epp_cti: std_logic_vector(2 downto 0); -- sequencial addressing
  signal epp_stb, epp_cyc, epp_ack, epp_we, epp_rnw, epp_buf_valid: std_logic;
  signal w2o_stb, rst_stb, la_stb: std_logic;
  signal w2o_cyc: std_logic;
  signal w2o_ack, rst_ack, la_ack: std_logic;
  signal epp_datW, epp_datR, w2o_dat, rst_dat, la_dat: std_logic_vector(7 downto 0);
  -- wishbone to OPB logic
  signal msel, mack: std_logic;
  signal mdrd, mdwr: std_logic_vector(0 to c_real_dwidth-1);
  signal mbe: std_logic_vector(0 to c_real_dwidth/8 -1);
  signal ma: std_logic_vector(0 to 31);
  -- constant opb_msb_adr: std_logic_vector(0 to c_opb_awidth-1):= (others=>'0');
  
  -- LA signals
  signal la_data: std_logic_vector(c_la_dwidth-1 downto 0);
  signal la_trig: std_logic_vector(c_la_twidth-1 downto 0);
  signal la_ce_trig: std_logic;
  signal la_std_data: std_logic_vector(63 downto 0); -- standard (internal) LA watch signals
  signal la_std_ce: std_logic_vector(0 to 4); -- clock enable standard signals
begin
  epp_sel<= s_rst when epp_adr(31 downto 4)= X"FFFFFFF" else -- address FFFF FFF0 to FFFF FFFF
     s_la when epp_adr(31 downto 16)= X"FFFF" and c_la_mwidth>=4 else  -- address FFFF 0000 to FFFF FFEF
	   s_w2o; 

  epp_ack<= w2o_ack or rst_ack or la_ack;
  epp_datR<= rst_dat when epp_sel=s_rst else
             la_dat when epp_sel=s_la else
	  		 w2o_dat;
  w2o_cyc<= epp_cyc when epp_sel=s_w2o else '0';
  rst_stb<= epp_stb when epp_sel=s_rst else '0';
  la_stb<= epp_stb when epp_sel=s_la else '0';	  
  w2o_stb<= epp_stb when epp_sel=s_w2o else '0';
	    
  pp:  epp
  	port map (clk_I=> OPB_clk, arst=> arst,
		-- WISHBONE interface
		adr_O=> epp_adr, buf_valid=> epp_buf_valid,
		we_O=> epp_we, cyc_O=> epp_cyc, stb_O=> epp_stb, ack_I=> epp_ack,
		dat_O=> epp_datW, dat_I=> epp_datR, cti_O=> epp_cti,
		-- external (PIN) signals connected to CPLD and Parallel Port (FPGA is a slave device to CPLD!)
		pp_dck=> pp_dck, pp_dwr=> pp_dwr, pp_drd=> pp_drd);
    
     
 epp_rnw<= not epp_we;	
 
 dwidth: epp_dwidth -- convert 8-bit to 16 or 32 bit data
  generic map(dwidth=>c_real_dwidth,  
       use_seqAddr=> c_use_seqAddr)
  port map(clk=> OPB_clk, arst=> arst,
        seqAddr=> epp_cyc, rnw=> epp_rnw, buf_valid=> epp_buf_valid,
        -- 8-bit data interface
        stb8=> w2o_stb, ack8=> w2o_ack, adr8=> epp_adr,
        din8=> epp_datW, dout8=>w2o_dat,
        -- dwidth data interface
        stb=> msel, ack=> mack, be=> mbe, adr=> ma,
        din=> mdrd, dout=> mdwr);

   
  master: opb_master
  generic map(opb_dwidth=> c_opb_dwidth, dwidth=> c_real_dwidth,
    opb_awidth=> c_opb_awidth, awidth=> 32, transfer_size=> 1)
    port map(clk=> OPB_clk, arst=> arst, 
		-- OPB Master interface
	    M_ABus => M_ABus, M_BE=> M_BE, M_RNW=> M_RNW, M_select=> M_select,
	    M_seqAddr=> M_seqAddr, M_busLock=> M_busLock,
	    M_DBus=> M_DBus, M_request=> M_request,
	    OPB_MGrant=> OPB_MGrant, OPB_pendReq=> OPB_pendReq,
	    OPB_DBus=> OPB_DBus, OPB_errAck=> OPB_errAck,
	    OPB_retry=> OPB_retry, OPB_timeout=> OPB_timeout, OPB_xferAck=> OPB_xferAck,
        -- internal simplified bus
        di=> mdwr,  do=> mdrd, be=> mbe, a=> ma, msb_adr=> gnd32,
        rnw=> epp_rnw, sel=> msel, seqAddr=> '0', ack=> mack);
   
  			
---------------------------------------------------------------------------
-- OPB reset (Sys_rst) register
rstp: process(arst, OPB_clk) begin
  if arst='1' then rst_dat(0)<= '0';
  elsif OPB_clk='1' and OPB_clk'event then
	if rst_stb='1' then
		rst_dat(0)<= epp_datW(0);
	end if;
  end if;
 end process;
 
 rst_ack<= rst_stb; -- always ready when selected
 SYS_rst<= rst_dat(0);
 rst_dat(7 downto 1)<= (others=> '0');
 
-----------------------------------------------------------------
-- logic analyser - do not generate logic analyser
  la0: if c_la_mwidth< 4 generate
    la_ack<= '0';
    la_dat<= (others=>'0');
  end generate;
  
  la1: if c_la_mwidth >= 4 generate -- instanciate Logic Analyser
	la: log_anal
      generic map (data_width=> c_la_dwidth, mem_adr_width=> c_la_mwidth, 
	  ce_dwidth=> c_la_ce_dwidth, ced_type=> c_la_ce_dtype,
	    adr_width=> la_awidth, trig_width=> c_la_twidth, two_clocks=> 0, 
        use_run_length_coding=> c_la_run_length_coding)
      port map (arst=> arst, clk=> OPB_clk,
        -- interface for logic analyser 
	    data=> la_data, ce_data=> la_ceDBus,
        trig=> la_trig, ce_trig=> la_ce_trig,
	    -- control WISHBOBE slave interface - interface for setting logic analyser options and transfering analysed data to computer
        wb_clk_I=> OPB_clk, 
	    wb_adr_I=> epp_adr(la_awidth-1 downto 0), wb_dat_I=> epp_datW, wb_dat_O=> la_dat,
	    wb_stb_I=> la_stb, wb_we_I=> epp_we,
	    wb_ack_O=> la_ack); 
    -- standard internal suignals to be analysed by the LA
	g32: if c_la_dwidth<=32 generate
	  la_std_data(7 downto 0)<= OPB_busLock & OPB_seqAddr & OPB_RNW & OPB_errAck 
        & OPB_timeout & OPB_rst & OPB_xferAck & OPB_select;
      g15: if c_la_dwidth=16 and c_la_run_length_coding=1 generate
        la_std_data(14 downto 8)<= OPB_DBus(0 to 6);
      end generate;
      gn15: if c_la_dwidth/=16 or c_la_run_length_coding=0 generate
        la_std_data(15 downto 8)<= OPB_DBus(0 to 7);
      end generate;
      la_std_data(31 downto 16)<= OPB_ABus(c_opb_awidth-16 to c_opb_awidth-1);
	end generate;
	g64: if c_la_dwidth=64 generate
	  la_std_data(7 downto 0)<= OPB_busLock & OPB_seqAddr & OPB_RNW & OPB_errAck 
	      & OPB_timeout & OPB_rst & OPB_xferAck & OPB_select;
      la_std_data(39 downto 8)<= OPB_DBus(0 to 31);
	  la_std_data(63 downto 40)<= OPB_ABus(c_opb_awidth-24 to c_opb_awidth-1);
	end generate;
   
	-- c_la_dtype (data type)
    dtype0: if c_la_dtype=0 generate -- internal logic
	    la_data<= la_std_data(c_la_dwidth-1 downto 0);
	end generate;
	dtype1: if c_la_dtype = 1 generate -- external data
	   la_data<= la_DBus;
	end generate;
	dtype2: if c_la_dtype = 2 generate -- LSB OPB_ABus
	   la_data<= OPB_ABus(c_opb_awidth-c_la_dwidth to c_opb_awidth-1); -- LSBs
	end generate;
	dtype3: if c_la_dtype = 3 generate -- MSB OPB_DBus
	   la_data<= OPB_DBus(0 to c_la_dwidth-1); -- MSBs
	end generate;
    -- c_la_ttype (triger type) -- trigger data type= 0- internal, 1- external, 2- OPB_ABus, 3- OPB_DBus 4- same as la_dbus
	ttype0: if c_la_ttype = 0 generate -- internal (same as internal data)
      la_trig<= la_std_data(c_la_twidth-1 downto 0);
	end generate;
	ttype1: if c_la_ttype = 1 generate -- external
	  la_trig<= la_TBus;
	end generate;
	ttype2: if c_la_ttype = 2 generate -- LSB OPB_ABus
	   la_trig<= OPB_ABus(c_opb_awidth-c_la_twidth to c_opb_awidth-1); -- LSBs
	end generate;
	ttype3: if c_la_ttype = 3 generate -- MSB OPB_DBus
	   la_trig<= OPB_DBus(0 to c_la_twidth-1); -- MSBs
	end generate;
	ttype4: if c_la_ttype = 4 generate -- same as la_DBus
	  la_trig<= la_DBus(0 to c_la_twidth-1);
	end generate;

	-- c_la_tce -- data clock enable= 0- always '1', 1 - external, 2- '1' when OPB_select='1'; 3 - '1' when OPB_xferAck='1', 4 - '1' when OPB_errAck='1' or OPB_xferAck or OPB_retry='1', 5 - OPB_rst
	la_std_ce(0 to 3)<= '1' & la_ceTBus & OPB_select & OPB_xferAck;
	la_std_ce(4)<= OPB_xferAck or OPB_errAck or OPB_retry or OPB_timeout;
    
    la_ce_trig<= la_std_ce(c_la_ce_ttype);
  end generate; -- include logic analyser
	  
-- global set/reset logic - this component draws rst during chip configuration only (no external reset is used)
 global_reset: ROC
	port map (O=> arst);
	
 assert c_real_dwidth<=c_opb_dwidth
   report "opb_epp error. c_real_dwidth must be greater than c_opb_dwidth"
   severity failure;
 
end opb_epp_arch;