lu20040094.tan.qmsg

组成原理实验作业

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 06 21:02:43 2007 " "Info: Processing started: Fri Apr 06 21:02:43 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off LU20040094 -c LU20040094 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off LU20040094 -c LU20040094" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES_NOT_SUPPORTED" "" "Warning: Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" {  } {  } 0 0 "Timing Analysis does not support the analysis of latches as synchronous elements for the currently selected device family" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "a\[1\] sum\[1\] 31.400 ns Longest " "Info: Longest tpd from source pin \"a\[1\]\" to destination pin \"sum\[1\]\" is 31.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns a\[1\] 1 PIN PIN_81 65 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_81; Fanout = 65; PIN Node = 'a\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { a[1] } "NODE_NAME" } } { "20040094.vhd" "" { Text "F:/vhdl 实验/实验一/20040094.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.000 ns) 6.000 ns lpm_add_sub:Add2\|addcore:adder\|addcore:adder\[0\]\|g3~8bal 2 COMB LC16 19 " "Info: 2: + IC(1.800 ns) + CELL(4.000 ns) = 6.000 ns; Loc. = LC16; Fanout = 19; COMB Node = 'lpm_add_sub:Add2\|addcore:adder\|addcore:adder\[0\]\|g3~8bal'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.800 ns" { a[1] lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~8bal } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 495 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(4.000 ns) 11.400 ns lpm_add_sub:Add2\|addcore:adder\|addcore:adder\[0\]\|g3~15 3 COMB LC21 43 " "Info: 3: + IC(1.400 ns) + CELL(4.000 ns) = 11.400 ns; Loc. = LC21; Fanout = 43; COMB Node = 'lpm_add_sub:Add2\|addcore:adder\|addcore:adder\[0\]\|g3~15'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.400 ns" { lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~8bal lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~15 } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 495 5 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(3.000 ns) 15.900 ns lpm_add_sub:Add4\|addcore:adder\|addcore:adder\[0\]\|ps\[3\]~41 4 COMB LC39 1 " "Info: 4: + IC(1.500 ns) + CELL(3.000 ns) = 15.900 ns; Loc. = LC39; Fanout = 1; COMB Node = 'lpm_add_sub:Add4\|addcore:adder\|addcore:adder\[0\]\|ps\[3\]~41'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.500 ns" { lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~15 lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~41 } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 169 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 18.000 ns lpm_add_sub:Add4\|addcore:adder\|addcore:adder\[0\]\|ps\[3\]~18 5 COMB LC40 30 " "Info: 5: + IC(0.000 ns) + CELL(2.100 ns) = 18.000 ns; Loc. = LC40; Fanout = 30; COMB Node = 'lpm_add_sub:Add4\|addcore:adder\|addcore:adder\[0\]\|ps\[3\]~18'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~41 lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~18 } "NODE_NAME" } } { "addcore.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/addcore.tdf" 169 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 22.400 ns bsum~158 6 COMB LC3 1 " "Info: 6: + IC(1.400 ns) + CELL(3.000 ns) = 22.400 ns; Loc. = LC3; Fanout = 1; COMB Node = 'bsum~158'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~18 bsum~158 } "NODE_NAME" } } { "20040094.vhd" "" { Text "F:/vhdl 实验/实验一/20040094.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 24.500 ns bsum~79 7 COMB LC4 9 " "Info: 7: + IC(0.000 ns) + CELL(2.100 ns) = 24.500 ns; Loc. = LC4; Fanout = 9; COMB Node = 'bsum~79'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { bsum~158 bsum~79 } "NODE_NAME" } } { "20040094.vhd" "" { Text "F:/vhdl 实验/实验一/20040094.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(3.000 ns) 28.900 ns bsum~164 8 COMB LC10 1 " "Info: 8: + IC(1.400 ns) + CELL(3.000 ns) = 28.900 ns; Loc. = LC10; Fanout = 1; COMB Node = 'bsum~164'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { bsum~79 bsum~164 } "NODE_NAME" } } { "20040094.vhd" "" { Text "F:/vhdl 实验/实验一/20040094.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 31.000 ns bsum~85 9 COMB LC11 1 " "Info: 9: + IC(0.000 ns) + CELL(2.100 ns) = 31.000 ns; Loc. = LC11; Fanout = 1; COMB Node = 'bsum~85'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { bsum~164 bsum~85 } "NODE_NAME" } } { "20040094.vhd" "" { Text "F:/vhdl 实验/实验一/20040094.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 31.400 ns sum\[1\] 10 PIN PIN_8 0 " "Info: 10: + IC(0.000 ns) + CELL(0.400 ns) = 31.400 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'sum\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.400 ns" { bsum~85 sum[1] } "NODE_NAME" } } { "20040094.vhd" "" { Text "F:/vhdl 实验/实验一/20040094.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.900 ns ( 76.11 % ) " "Info: Total cell delay = 23.900 ns ( 76.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 23.89 % ) " "Info: Total interconnect delay = 7.500 ns ( 23.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "31.400 ns" { a[1] lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~8bal lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~15 lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~41 lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~18 bsum~158 bsum~79 bsum~164 bsum~85 sum[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "31.400 ns" { a[1] a[1]~out lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~8bal lpm_add_sub:Add2|addcore:adder|addcore:adder[0]|g3~15 lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~41 lpm_add_sub:Add4|addcore:adder|addcore:adder[0]|ps[3]~18 bsum~158 bsum~79 bsum~164 bsum~85 sum[1] } { 0.000ns 0.000ns 1.800ns 1.400ns 1.500ns 0.000ns 1.400ns 0.000ns 1.400ns 0.000ns 0.000ns } { 0.000ns 0.200ns 4.000ns 4.000ns 3.000ns 2.100ns 3.000ns 2.100ns 3.000ns 2.100ns 0.400ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Apr 06 21:02:43 2007 " "Info: Processing ended: Fri Apr 06 21:02:43 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}