lu20040094.rpt

组成原理实验作业用VHDL实现的六层电梯程序

137  -> - - - - - - - - - - * | - * - * - - - - | <-- bn12
133  -> - * - * - - - - - - - | - - - * - - - * | <-- s0
132  -> - * - * - - - - - - - | - - - * - - - * | <-- s1
131  -> - - * - - - - - - - - | - - - * - - - * | <-- s2
5    -> - - * - - - - - - - - | - - - * - - - * | <-- s3
6    -> - - - - * - * - - - - | - - - * - - * - | <-- s4
8    -> - - - - * - * - - - - | - - - * - - * - | <-- s5
9    -> - - - - - * - - - - - | - - - * - - * - | <-- s6
10   -> - - - - - * - - - - - | - - - * - - * - | <-- s7
16   -> - - - - - - - * - * - | - - - * - * - - | <-- s8
88   -> - - - - - - - * - * - | - - - * - * - - | <-- s9
15   -> - - - - - - - - * - - | - - - * - * - - | <-- s10
11   -> - - - - - - - - * - - | - - - * - * - - | <-- s11
140  -> - - - - - - - - - - * | - - - * * - - - | <-- s12
143  -> - - - - - - - - - - * | - - - * * - - - | <-- s13
LC118-> * - - - - - - - - - - | - - - * - - - - | <-- fn0
LC120-> * - - - - - - - - - - | - - - * - - - - | <-- fn1
LC117-> * - - - - - - - - - - | - - - * - - - - | <-- fn2
LC123-> * - - - - - - - - - - | - - - * - - - - | <-- fn3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        e:\max plus\lu20040094.rpt
lu20040094

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'E':

                                         Logic cells placed in LAB 'E'
        +------------------------------- LC70 cn16
        | +----------------------------- LC68 fn12
        | | +--------------------------- LC65 fn13
        | | | +------------------------- LC69 fn14
        | | | | +----------------------- LC72 fn15
        | | | | | +--------------------- LC77 gn3
        | | | | | | +------------------- LC67 pn3
        | | | | | | | +----------------- LC73 |74181:adderx4|:39
        | | | | | | | | +--------------- LC74 |74181:adderx4|:40
        | | | | | | | | | +------------- LC75 |74181:adderx4|:41
        | | | | | | | | | | +----------- LC76 |74181:adderx4|:42
        | | | | | | | | | | | +--------- LC78 |74181:adderx4|:49
        | | | | | | | | | | | | +------- LC79 |74181:adderx4|:50
        | | | | | | | | | | | | | +----- LC80 |74181:adderx4|:76
        | | | | | | | | | | | | | | +--- LC66 |74181:adderx4|:88
        | | | | | | | | | | | | | | | +- LC71 |74181:adderx4|:89
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'E'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'E':
LC73 -> * - * - - * - - - - - - - * - * | - - - - * - - - | <-- |74181:adderx4|:39
LC74 -> * - * - - * * - - - - - - * - * | - - - - * - - - | <-- |74181:adderx4|:40
LC75 -> * - - * - * - - - - - - - * - - | - - - - * - - - | <-- |74181:adderx4|:41
LC76 -> * - - * - * * - - - - - - * - - | - - - - * - - - | <-- |74181:adderx4|:42
LC78 -> * - - - * * * - - - - - - - - - | - - - - * - - - | <-- |74181:adderx4|:49
LC79 -> * - - - * * - - - - - - - - - - | - - - - * - - - | <-- |74181:adderx4|:50
LC80 -> - - - - * - - - - - - - - - - - | - - - - * - - - | <-- |74181:adderx4|:76
LC66 -> - - * - - - - - - - - - - - - - | - - - - * - - - | <-- |74181:adderx4|:88
LC71 -> - - - * - - - - - - - - - - - - | - - - - * - - - | <-- |74181:adderx4|:89

Pin
69   -> - - * - - - - * * - - - - - - - | - - - - * - - - | <-- an13
68   -> - - - * - - - - - * * - - - - - | - - - - * - - - | <-- an14
87   -> - - - - * - - - - - - * * - - - | - - - - * - - - | <-- an15
97   -> - - * - - - - * * - - - - - - - | - - - - * - - - | <-- bn13
29   -> - - - * - - - - - * * - - - - - | - - - - * - - - | <-- bn14
27   -> - - - - * - - - - - - * * - - - | - - - - * - - - | <-- bn15
23   -> - * - - - - - - - - - - - * * * | - - - - * - - - | <-- m3
140  -> - - - - - - - * - * - - * - - - | - - - * * - - - | <-- s12
143  -> - - - - - - - * - * - - * - - - | - - - * * - - - | <-- s13
142  -> - - * * * - - - * - * * - - - - | - * - - * - - - | <-- s14
141  -> - - * * * - - - * - * * - - - - | - * - - * - - - | <-- s15
LC87 -> * * - - - - - - - - - - - * * * | - - - - * - - - | <-- connection3
LC52 -> * * - - - * - - - - - - - * * * | - - - - * - - - | <-- |74181:adderx4|:37
LC22 -> * * - - - - * - - - - - - * * * | - - - - * - - - | <-- |74181:adderx4|:38


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        e:\max plus\lu20040094.rpt
lu20040094

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'F':

                                         Logic cells placed in LAB 'F'
        +------------------------------- LC85 cn12
        | +----------------------------- LC87 connection3
        | | +--------------------------- LC83 fn8
        | | | +------------------------- LC84 fn9
        | | | | +----------------------- LC91 fn10
        | | | | | +--------------------- LC81 fn11
        | | | | | | +------------------- LC86 gn2
        | | | | | | | +----------------- LC88 pn2
        | | | | | | | | +--------------- LC92 |74181:adderx3|:40
        | | | | | | | | | +------------- LC90 |74181:adderx3|:41
        | | | | | | | | | | +----------- LC82 |74181:adderx3|:42
        | | | | | | | | | | | +--------- LC94 |74181:adderx3|:49
        | | | | | | | | | | | | +------- LC93 |74181:adderx3|:50
        | | | | | | | | | | | | | +----- LC95 |74181:adderx3|:76
        | | | | | | | | | | | | | | +--- LC96 |74181:adderx3|:88
        | | | | | | | | | | | | | | | +- LC89 |74181:adderx3|:89
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'F'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'F':
LC92 -> * * - * - - * * - - - - - * - * | - - - - - * - - | <-- |74181:adderx3|:40
LC90 -> * * - - * - * - - - - - - * - - | - - - - - * - - | <-- |74181:adderx3|:41
LC82 -> * * - - * - * * - - - - - * - - | - - - - - * - - | <-- |74181:adderx3|:42
LC94 -> * * - - - * * * - - - - - - - - | - - - - - * - - | <-- |74181:adderx3|:49
LC93 -> * * - - - * * - - - - - - - - - | - - - - - * - - | <-- |74181:adderx3|:50
LC95 -> - - - - - * - - - - - - - - - - | - - - - - * - - | <-- |74181:adderx3|:76
LC96 -> - - - * - - - - - - - - - - - - | - - - - - * - - | <-- |74181:adderx3|:88
LC89 -> - - - - * - - - - - - - - - - - | - - - - - * - - | <-- |74181:adderx3|:89

Pin
28   -> - - - * - - - - * - - - - - - - | - - - * - * - - | <-- an9
39   -> - - - - * - - - - * * - - - - - | - - - - - * - - | <-- an10
41   -> - - - - - * - - - - - * * - - - | - - - - - * - - | <-- an11
134  -> - - - * - - - - * - - - - - - - | - - - * - * - - | <-- bn9
7    -> - - - - * - - - - * * - - - - - | - - - - - * - - | <-- bn10
83   -> - - - - - * - - - - - * * - - - | - - - - - * - - | <-- bn11
22   -> - - * - - - - - - - - - - * * * | - - - - - * - - | <-- m2
16   -> - - - - - - - - - * - - * - - - | - - - * - * - - | <-- s8
88   -> - - - - - - - - - * - - * - - - | - - - * - * - - | <-- s9
15   -> - - - * * * - - * - * * - - - - | - - - * - * - - | <-- s10
11   -> - - - * * * - - * - * * - - - - | - - - * - * - - | <-- s11
LC111-> * * * - - - - - - - - - - * * * | - - - - - * - - | <-- connection2
LC56 -> * * * - - - * - - - - - - * * * | - - - - - * - - | <-- |74181:adderx3|:37
LC54 -> * * * - - - - * - - - - - * * * | - - - - - * - - | <-- |74181:adderx3|:38
LC53 -> * * - * - - * - - - - - - * - * | - - - - - * - - | <-- |74181:adderx3|:39


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        e:\max plus\lu20040094.rpt
lu20040094

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'G':

                                         Logic cells placed in LAB 'G'
        +------------------------------- LC110 cn8
        | +----------------------------- LC111 connection2
        | | +--------------------------- LC99 fn4
        | | | +------------------------- LC107 fn5
        | | | | +----------------------- LC105 fn6
        | | | | | +--------------------- LC102 fn7
        | | | | | | +------------------- LC101 gn1
        | | | | | | | +----------------- LC97 pn1
        | | | | | | | | +--------------- LC112 |74181:adderx2|:40
        | | | | | | | | | +------------- LC98 |74181:adderx2|:41
        | | | | | | | | | | +----------- LC104 |74181:adderx2|:42
        | | | | | | | | | | | +--------- LC106 |74181:adderx2|:49
        | | | | | | | | | | | | +------- LC100 |74181:adderx2|:50
        | | | | | | | | | | | | | +----- LC103 |74181:adderx2|:76
        | | | | | | | | | | | | | | +--- LC109 |74181:adderx2|:88
        | | | | | | | | | | | | | | | +- LC108 |74181:adderx2|:89
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'G'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'G':
LC112-> * * - * - - * * - - - - - * - * | - - - - - - * - | <-- |74181:adderx2|:40
LC98 -> * * - - * - * - - - - - - * - - | - - - - - - * - | <-- |74181:adderx2|:41
LC104-> * * - - * - * * - - - - - * - - | - - - - - - * - | <-- |74181:adderx2|:42
LC106-> * * - - - * * * - - - - - - - - | - - - - - - * - | <-- |74181:adderx2|:49
LC100-> * * - - - * * - - - - - - - - - | - - - - - - * - | <-- |74181:adderx2|:50
LC103-> - - - - - * - - - - - - - - - - | - - - - - - * - | <-- |74181:adderx2|:76
LC109-> - - - * - - - - - - - - - - - - | - - - - - - * - | <-- |74181:adderx2|:88
LC108-> - - - - * - - - - - - - - - - - | - - - - - - * - | <-- |74181:adderx2|:89

Pin
14   -> - - - * - - - - * - - - - - - - | - - - * - - * - | <-- an5
40   -> - - - - * - - - - * * - - - - - | - - - - - - * - | <-- an6
44   -> - - - - - * - - - - - * * - - - | - - - - - - * - | <-- an7
136  -> - - - * - - - - * - - - - - - - | - - - * - - * - | <-- bn5
70   -> - - - - * - - - - * * - - - - - | - - - - - - * - | <-- bn6
54   -> - - - - - * - - - - - * * - - - | - - - - - - * - | <-- bn7
21   -> - - * - - - - - - - - - - * * * | - - - - - - * - | <-- m1
6    -> - - - - - - - - - * - - * - - - | - - - * - - * - | <-- s4
8    -> - - - - - - - - - * - - * - - - | - - - * - - * - | <-- s5
9    -> - - - * * * - - * - * * - - - - | - - - * - - * - | <-- s6
10   -> - - - * * * - - * - * * - - - - | - - - * - - * - | <-- s7
LC128-> * * * - - - - - - - - - - * * * | - - - - - - * - | <-- connection1
LC57 -> * * * - - - * - - - - - - * * * | - - - - - - * - | <-- |74181:adderx2|:37
LC61 -> * * * - - - - * - - - - - * * * | - - - - - - * - | <-- |74181:adderx2|:38
LC63 -> * * - * - - * - - - - - - * - * | - - - - - - * - | <-- |74181:adderx2|:39


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                        e:\max plus\lu20040094.rpt
lu20040094

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'H':

                                         Logic cells placed in LAB 'H'
        +------------------------------- LC115 cn4
        | +----------------------------- LC128 connection1
        | | +--------------------------- LC118 fn0
        | | | +------------------------- LC120 fn1
        | | | | +----------------------- LC117 fn2
        | | | | | +--------------------- LC123 fn3
        | | | | | | +------------------- LC113 gn0
        | | | | | | | +----------------- LC116 pn0
        | | | | | | | | +--------------- LC125 |74181:adderx1|:40
        | | | | | | | | | +------------- LC119 |74181:adderx1|:41
        | | | | | | | | | | +----------- LC114 |74181:adderx1|:42
        | | | | | | | | | | | +--------- LC127 |74181:adderx1|:49
        | | | | | | | | | | | | +------- LC126 |74181:adderx1|:50
        | | | | | | | | | | | | | +----- LC124 |74181:adderx1|:76
        | | | | | | | | | | | | | | +--- LC122 |74181:adderx1|:88
        | | | | | | | | | | | | | | | +- LC121 |74181:adderx1|:89
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'H'
LC      | | | | | | | | | | | | | | | | | A B C D E F G H |     Logic cells that feed LAB 'H':
LC125-> * * - * - - * * - - - - - * - * | - - - - - - - * | <-- |74181:adderx1|:40
LC119-> * * - - * - * - - - - - - * - - | - - - - - - - * | <-- |74181:adderx1|:41
LC114-> * * - - * - * * - - - - - * - - | - - - - - - - * | <-- |74181:adderx1|:42
LC127-> * * - - - * * * - - - - - - - - | - - - - - - - * | <-- |74181:adderx1|:49
LC126-> * * - - - * * - - - - - - - - - | - - - - - - - * | <-- |74181:adderx1|:50
LC124-> - - - - - * - - - - - - - - - - | - - - - - - - * | <-- |74181:adderx1|:76
LC122-> - - - * - - - - - - - - - - - - | - - - - - - - * | <-- |74181:adderx1|:88
LC121-> - - - - * - - - - - - - - - - - | - - - - - - - * | <-- |74181:adderx1|:89

Pin
18   -> - - - * - - - - * - - - - - - - | - - - * - - - * | <-- an1
72   -> - - - - * - - - - * * - - - - - | - - - - - - - * | <-- an2
37   -> - - - - - * - - - - - * * - - - | - - - - - - - * | <-- an3
138  -> - - - * - - - - * - - - - - - - | - - - * - - - * | <-- bn1
42   -> - - - - * - - - - * * - - - - - | - - - - - - - * | <-- bn2
45   -> - - - - - * - - - - - * * - - - | - - - - - - - * | <-- bn3
26   -> * * * - - - - - - - - - - * * * | - - - - - - - * | <-- ci
74   -> - - * - - - - - - - - - - * * * | - - - - - - - * | <-- m0
133  -> - - - - - - - - - * - - * - - - | - - - * - - - * | <-- s0
132  -> - - - - - - - - - * - - * - - - | - - - * - - - * | <-- s1
131  -> - - - * * * - - * - * * - - - - | - - - * - - - * | <-- s2