📄 lu20040094.rpt
字号:
15 (20) (B) INPUT 0 0 0 0 0 3 4 s10
11 (22) (B) INPUT 0 0 0 0 0 3 4 s11
140 (5) (A) INPUT 0 0 0 0 0 0 4 s12
143 (1) (A) INPUT 0 0 0 0 0 0 4 s13
142 (3) (A) INPUT 0 0 0 0 0 3 4 s14
141 (4) (A) INPUT 0 0 0 0 0 3 4 s15
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
Device-Specific Information: e:\max plus\lu20040094.rpt
lu20040094
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
56 49 D OUTPUT t 0 0 0 0 4 0 0 aeqb0
30 36 C OUTPUT t 0 0 0 0 4 0 0 aeqb1
31 35 C OUTPUT t 0 0 0 0 4 0 0 aeqb2
32 33 C OUTPUT t 0 0 0 0 4 0 0 aeqb3
107 115 H OUTPUT t 1 0 1 1 8 0 0 cn4
102 110 G OUTPUT t 1 0 1 0 9 0 0 cn8
80 85 F OUTPUT t 1 0 1 0 9 0 0 cn12
65 70 E OUTPUT t 1 0 1 0 9 0 0 cn16
111 118 H OUTPUT t 0 0 0 2 2 1 0 fn0
112 120 H OUTPUT t 0 0 0 4 3 1 0 fn1
110 117 H OUTPUT t 0 0 0 4 3 1 0 fn2
114 123 H OUTPUT t 0 0 0 4 3 1 0 fn3
92 99 G OUTPUT t 0 0 0 1 3 1 0 fn4
99 107 G OUTPUT t 0 0 0 4 3 1 0 fn5
98 105 G OUTPUT t 0 0 0 4 3 1 0 fn6
96 102 G OUTPUT t 0 0 0 4 3 1 0 fn7
78 83 F OUTPUT t 0 0 0 1 3 1 0 fn8
79 84 F OUTPUT t 0 0 0 4 3 1 0 fn9
84 91 F OUTPUT t 0 0 0 4 3 1 0 fn10
77 81 F OUTPUT t 0 0 0 4 3 1 0 fn11
62 68 E OUTPUT t 0 0 0 1 3 1 0 fn12
60 65 E OUTPUT t 0 0 0 4 3 1 0 fn13
63 69 E OUTPUT t 0 0 0 4 3 1 0 fn14
67 72 E OUTPUT t 0 0 0 4 3 1 0 fn15
106 113 H OUTPUT t 0 0 0 0 7 0 0 gn0
94 101 G OUTPUT t 0 0 0 0 7 0 0 gn1
81 86 F OUTPUT t 0 0 0 0 7 0 0 gn2
71 77 E OUTPUT t 0 0 0 0 7 0 0 gn3
109 116 H OUTPUT t 0 0 0 0 4 0 0 pn0
91 97 G OUTPUT t 0 0 0 0 4 0 0 pn1
82 88 F OUTPUT t 0 0 0 0 4 0 0 pn2
61 67 E OUTPUT t 0 0 0 0 4 0 0 pn3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
Device-Specific Information: e:\max plus\lu20040094.rpt
lu20040094
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(119) 128 H SOFT t 1 0 1 1 8 2 4 connection1
- 111 G SOFT t 1 0 1 0 9 2 4 connection2
- 87 F SOFT t 1 0 1 0 9 2 3 connection3
- 55 D SOFT t 0 0 0 4 0 3 4 |74181:adderx1|:37
- 50 D SOFT t 0 0 0 4 0 3 4 |74181:adderx1|:38
(40) 60 D SOFT t 0 0 0 4 0 3 3 |74181:adderx1|:39
(117) 125 H SOFT t 0 0 0 4 0 4 3 |74181:adderx1|:40
- 119 H SOFT t 0 0 0 4 0 3 2 |74181:adderx1|:41
- 114 H SOFT t 0 0 0 4 0 4 2 |74181:adderx1|:42
- 127 H SOFT t 0 0 0 4 0 4 1 |74181:adderx1|:49
(118) 126 H SOFT t 0 0 0 4 0 3 1 |74181:adderx1|:50
(116) 124 H SOFT t 0 0 0 2 6 1 0 |74181:adderx1|:76
- 122 H SOFT t 0 0 0 2 2 1 0 |74181:adderx1|:88
(113) 121 H SOFT t 0 0 0 2 4 1 0 |74181:adderx1|:89
(42) 57 D SOFT t 0 0 0 4 0 3 4 |74181:adderx2|:37
(39) 61 D SOFT t 0 0 0 4 0 3 4 |74181:adderx2|:38
- 63 D SOFT t 0 0 0 4 0 3 3 |74181:adderx2|:39
(104) 112 G SOFT t 0 0 0 4 0 4 3 |74181:adderx2|:40
- 98 G SOFT t 0 0 0 4 0 3 2 |74181:adderx2|:41
(97) 104 G SOFT t 0 0 0 4 0 4 2 |74181:adderx2|:42
- 106 G SOFT t 0 0 0 4 0 4 1 |74181:adderx2|:49
(93) 100 G SOFT t 0 0 0 4 0 3 1 |74181:adderx2|:50
- 103 G SOFT t 0 0 0 1 7 1 0 |74181:adderx2|:76
(101) 109 G SOFT t 0 0 0 1 3 1 0 |74181:adderx2|:88
(100) 108 G SOFT t 0 0 0 1 5 1 0 |74181:adderx2|:89
(44) 56 D SOFT t 0 0 0 4 0 3 4 |74181:adderx3|:37
(45) 54 D SOFT t 0 0 0 4 0 3 4 |74181:adderx3|:38
(53) 53 D SOFT t 0 0 0 4 0 3 3 |74181:adderx3|:39
(86) 92 F SOFT t 0 0 0 4 0 4 3 |74181:adderx3|:40
- 90 F SOFT t 0 0 0 4 0 3 2 |74181:adderx3|:41
- 82 F SOFT t 0 0 0 4 0 4 2 |74181:adderx3|:42
(88) 94 F SOFT t 0 0 0 4 0 4 1 |74181:adderx3|:49
(87) 93 F SOFT t 0 0 0 4 0 3 1 |74181:adderx3|:50
- 95 F SOFT t 0 0 0 1 7 1 0 |74181:adderx3|:76
(89) 96 F SOFT t 0 0 0 1 3 1 0 |74181:adderx3|:88
(83) 89 F SOFT t 0 0 0 1 5 1 0 |74181:adderx3|:89
(54) 52 D SOFT t 0 0 0 4 0 3 3 |74181:adderx4|:37
(11) 22 B SOFT t 0 0 0 4 0 3 3 |74181:adderx4|:38
(68) 73 E SOFT t 0 0 0 4 0 3 2 |74181:adderx4|:39
- 74 E SOFT t 0 0 0 4 0 4 2 |74181:adderx4|:40
(69) 75 E SOFT t 0 0 0 4 0 3 1 |74181:adderx4|:41
(70) 76 E SOFT t 0 0 0 4 0 4 1 |74181:adderx4|:42
(72) 78 E SOFT t 0 0 0 4 0 4 0 |74181:adderx4|:49
- 79 E SOFT t 0 0 0 4 0 3 0 |74181:adderx4|:50
(74) 80 E SOFT t 0 0 0 1 7 1 0 |74181:adderx4|:76
- 66 E SOFT t 0 0 0 1 3 1 0 |74181:adderx4|:88
- 71 E SOFT t 0 0 0 1 5 1 0 |74181:adderx4|:89
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
h = Register powers up high
Device-Specific Information: e:\max plus\lu20040094.rpt
lu20040094
** I/O STANDARDS **
Dedicated Pins in Pins in
I/O Standard Input Ref Input Pins I/O Bank 1 I/O Bank 2 Total
LVTTL - 0 46 39 85
Total VCCIO Current is 128 ma (Limit is 1200 ma)
Total GNDIO Current is 128 ma (Limit is 1200 ma)
IOVCC VCCIO VCCIO Current
Group I/O Pins Voltage Current Limit
A: 12/12(100%) 3.3V 0 ma / 100 ma ( 0%)
B: 14/16( 87%) 3.3V 0 ma / 200 ma ( 0%)
C: 16/16(100%) 3.3V 12 ma / 200 ma ( 6%)
D: 4/ 4(100%) 3.3V 4 ma / 100 ma ( 4%)
E: 12/12(100%) 3.3V 28 ma / 100 ma ( 28%)
F: 15/16( 93%) 3.3V 40 ma / 200 ma ( 20%)
G: 12/16( 75%) 3.3V 44 ma / 200 ma ( 22%)
H: 0/ 4( 0%) 3.3V 0 ma / 100 ma ( 0%)
IOGND GNDIO Current
Group I/O Pins Current Limit
A: 11/16( 68%) 28 ma / 200 ma ( 14%)
B: 15/16( 93%) 0 ma / 200 ma ( 0%)
C: 15/16( 93%) 12 ma / 200 ma ( 6%)
D: 16/16(100%) 20 ma / 200 ma ( 10%)
E: 16/16(100%) 40 ma / 200 ma ( 20%)
F: 12/16( 75%) 28 ma / 200 ma ( 14%)
IOVCC group A: VCCIO Current is 0 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
131 INPUT - LVTTL - - s2
132 INPUT - LVTTL - - s1
133 INPUT - LVTTL - - s0
134 INPUT - LVTTL - - bn9
136 INPUT - LVTTL - - bn5
137 INPUT - LVTTL - - bn12
138 INPUT - LVTTL - - bn1
139 INPUT - LVTTL - - an12
140 INPUT - LVTTL - - s12
141 INPUT - LVTTL - - s15
142 INPUT - LVTTL - - s14
143 INPUT - LVTTL - - s13
IOVCC group B: VCCIO Current is 0 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
5 INPUT - LVTTL - - s3
6 INPUT - LVTTL - - s4
7 INPUT - LVTTL - - bn10
8 INPUT - LVTTL - - s5
9 INPUT - LVTTL - - s6
10 INPUT - LVTTL - - s7
11 INPUT - LVTTL - - s11
14 INPUT - LVTTL - - an5
15 INPUT - LVTTL - - s10
16 INPUT - LVTTL - - s8
18 INPUT - LVTTL - - an1
21 INPUT - LVTTL - - m1
22 INPUT - LVTTL - - m2
23 INPUT - LVTTL - - m3
IOVCC group C: VCCIO Current is 12 ma (Limit is 200 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
25 INPUT - LVTTL - - bn8
26 INPUT - LVTTL - - ci
27 INPUT - LVTTL - - bn15
28 INPUT - LVTTL - - an9
29 INPUT - LVTTL - - bn14
30 OUTPUT 3.3V LVTTL - 4 ma aeqb1
31 OUTPUT 3.3V LVTTL - 4 ma aeqb2
32 OUTPUT 3.3V LVTTL - 4 ma aeqb3
37 INPUT - LVTTL - - an3
38 INPUT - LVTTL - - an4
39 INPUT - LVTTL - - an10
40 INPUT - LVTTL - - an6
41 INPUT - LVTTL - - an11
42 INPUT - LVTTL - - bn2
44 INPUT - LVTTL - - an7
45 INPUT - LVTTL - - bn3
IOVCC group D: VCCIO Current is 4 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
53 INPUT - LVTTL - - an8
54 INPUT - LVTTL - - bn7
55 INPUT - LVTTL - - bn4
56 OUTPUT 3.3V LVTTL - 4 ma aeqb0
IOVCC group E: VCCIO Current is 28 ma (Limit is 100 ma)
Pin Type Code VCCIO I/O Standard Input Ref Current Name
60 OUTPUT 3.3V LVTTL - 4 ma fn13
61 OUTPUT 3.3V LVTTL - 4 ma pn3
62 OUTPUT 3.3V LVTTL - 4 ma fn12
63 OUTPUT 3.3V LVTTL - 4 ma fn14
65 OUTPUT 3.3V LVTTL - 4 ma cn16
67 OUTPUT 3.3V LVTTL - 4 ma fn15
68 INPUT - LVTTL - - an14
69 INPUT - LVTTL - - an13
70 INPUT - LVTTL - - bn6
71 OUTPUT 3.3V LVTTL - 4 ma gn3
72 INPUT - LVTTL - - an2
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -