📄 lu20040094.rpt
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Project Information e:\max plus\lu20040094.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 07/23/2007 15:39:32
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
LU20040094
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
lu20040094
EPM7128BTC144-4 53 32 0 79 0 61 %
User Pins: 53 32 0
Project Information e:\max plus\lu20040094.rpt
** FILE HIERARCHY **
|74181:adderx1|
|74181:adderx2|
|74181:adderx3|
|74181:adderx4|
Device-Specific Information: e:\max plus\lu20040094.rpt
lu20040094
***** Logic for device 'lu20040094' compiled without errors.
Device: EPM7128BTC144-4
Device Options:
Turbo Bit = ON
Security Bit = OFF
Enable JTAG Support = ON
User Code = ffffffff
Device-Specific Information: e:\max plus\lu20040094.rpt
lu20040094
** ERROR SUMMARY **
Info: Chip 'lu20040094' in device 'EPM7128BTC144-4' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
V V V V
C C C C
C a b C C N N N G G G G C G
I s s s s n b n b G b I G G G G G G I . . . N N N N I f N f f f p
O 1 1 1 1 1 n 1 n N n s s s N N N N N N N N C C C D D D D O n D n n n n
1 3 4 5 2 2 1 2 5 D 9 0 1 2 T D D D D D D T . . . * * * * 2 3 * 1 0 2 0
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
N.C. | 1 108 | N.C.
N.C. | 2 107 | cn4
GND | 3 106 | gn0
#TDI | 4 105 | GND
s3 | 5 104 | #TDO
s4 | 6 103 | N.C.
bn10 | 7 102 | cn8
s5 | 8 101 | GND*
s6 | 9 100 | GND*
s7 | 10 99 | fn5
s11 | 11 98 | fn6
N.C. | 12 97 | bn13
GND | 13 96 | fn7
an5 | 14 95 | VCCIO2
s10 | 15 94 | gn1
s8 | 16 93 | bn0
GND | 17 92 | fn4
an1 | 18 91 | pn1
N.C. | 19 EPM7128BTC144-4 90 | N.C.
#TMS | 20 89 | #TCK
m1 | 21 88 | s9
m2 | 22 87 | an15
m3 | 23 86 | an0
VCCIO1 | 24 85 | GND
bn8 | 25 84 | fn10
ci | 26 83 | bn11
bn15 | 27 82 | pn2
an9 | 28 81 | gn2
bn14 | 29 80 | cn12
aeqb1 | 30 79 | fn9
aeqb2 | 31 78 | fn8
aeqb3 | 32 77 | fn11
GND | 33 76 | VCCIO2
N.C. | 34 75 | N.C.
N.C. | 35 74 | m0
N.C. | 36 73 | VCCIO2
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
a a a a a b N a b N N N N V V G a b b a G V G f p f f G c N f a a b g a
n n n n n n . n n . . . . C C N n n n e N C N n n n n N n . n n n n n n
3 4 1 6 1 2 C 7 3 C C C C C C D 8 7 4 q D C D 1 3 1 1 D 1 C 1 1 1 6 3 2
0 1 . . . . . I I b I 3 2 4 6 . 5 4 3
O N 0 N
1 T T
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO1 = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
VCCIO2 = Dedicated power pin, which MUST be connected to VCC (3.3 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GND* = These I/O pins can either be left unconnected or connected to GND. Connecting these pins to GND will improve the device's immunity to noise.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: e:\max plus\lu20040094.rpt
lu20040094
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 12/12(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 1/16( 6%) 12/12(100%) 0/16( 0%) 4/36( 11%)
C: LC33 - LC48 3/16( 18%) 12/12(100%) 0/16( 0%) 12/36( 33%)
D: LC49 - LC64 11/16( 68%) 12/12(100%) 0/16( 0%) 32/36( 88%)
E: LC65 - LC80 16/16(100%) 12/12(100%) 1/16( 6%) 23/36( 63%)
F: LC81 - LC96 16/16(100%) 12/12(100%) 2/16( 12%) 23/36( 63%)
G: LC97 - LC112 16/16(100%) 10/12( 83%) 2/16( 12%) 23/36( 63%)
H: LC113 - LC128 16/16(100%) 7/12( 58%) 2/16( 12%) 23/36( 63%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 89/96 ( 92%)
Total logic cells used: 79/128 ( 61%)
Total shareable expanders used: 0/128 ( 0%)
Total Turbo logic cells used: 79/128 ( 61%)
Total shareable expanders not available (n/a): 7/128 ( 5%)
Average fan-in: 5.35
Total fan-in: 423
Total input pins required: 53
Total output pins required: 32
Total bidirectional pins required: 0
Total reserved pins required 4
Total logic cells required: 79
Total flipflops required: 0
Total product terms required: 239
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 0/ 128 ( 0%)
Device-Specific Information: e:\max plus\lu20040094.rpt
lu20040094
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
86 (92) (F) INPUT 0 0 0 0 0 0 2 an0
18 (17) (B) INPUT 0 0 0 0 0 1 2 an1
72 (78) (E) INPUT 0 0 0 0 0 1 2 an2
37 (64) (D) INPUT 0 0 0 0 0 1 2 an3
38 (62) (D) INPUT 0 0 0 0 0 0 2 an4
14 (21) (B) INPUT 0 0 0 0 0 1 2 an5
40 (60) (D) INPUT 0 0 0 0 0 1 2 an6
44 (56) (D) INPUT 0 0 0 0 0 1 2 an7
53 (53) (D) INPUT 0 0 0 0 0 0 2 an8
28 (38) (C) INPUT 0 0 0 0 0 1 2 an9
39 (61) (D) INPUT 0 0 0 0 0 1 2 an10
41 (59) (D) INPUT 0 0 0 0 0 1 2 an11
139 (6) (A) INPUT 0 0 0 0 0 0 2 an12
69 (75) (E) INPUT 0 0 0 0 0 1 2 an13
68 (73) (E) INPUT 0 0 0 0 0 1 2 an14
87 (93) (F) INPUT 0 0 0 0 0 1 2 an15
93 (100) (G) INPUT 0 0 0 0 0 0 2 bn0
138 (8) (A) INPUT 0 0 0 0 0 1 2 bn1
42 (57) (D) INPUT 0 0 0 0 0 1 2 bn2
45 (54) (D) INPUT 0 0 0 0 0 1 2 bn3
55 (51) (D) INPUT 0 0 0 0 0 0 2 bn4
136 (11) (A) INPUT 0 0 0 0 0 1 2 bn5
70 (76) (E) INPUT 0 0 0 0 0 1 2 bn6
54 (52) (D) INPUT 0 0 0 0 0 1 2 bn7
25 (43) (C) INPUT 0 0 0 0 0 0 2 bn8
134 (12) (A) INPUT 0 0 0 0 0 1 2 bn9
7 (28) (B) INPUT 0 0 0 0 0 1 2 bn10
83 (89) (F) INPUT 0 0 0 0 0 1 2 bn11
137 (9) (A) INPUT 0 0 0 0 0 0 2 bn12
97 (104) (G) INPUT 0 0 0 0 0 1 2 bn13
29 (37) (C) INPUT 0 0 0 0 0 1 2 bn14
27 (40) (C) INPUT 0 0 0 0 0 1 2 bn15
26 (41) (C) INPUT 0 0 0 0 0 2 4 ci
74 (80) (E) INPUT 0 0 0 0 0 1 3 m0
21 (46) (C) INPUT 0 0 0 0 0 1 3 m1
22 (45) (C) INPUT 0 0 0 0 0 1 3 m2
23 (44) (C) INPUT 0 0 0 0 0 1 3 m3
133 (13) (A) INPUT 0 0 0 0 0 0 4 s0
132 (14) (A) INPUT 0 0 0 0 0 0 4 s1
131 (16) (A) INPUT 0 0 0 0 0 3 4 s2
5 (30) (B) INPUT 0 0 0 0 0 3 4 s3
6 (29) (B) INPUT 0 0 0 0 0 0 4 s4
8 (27) (B) INPUT 0 0 0 0 0 0 4 s5
9 (25) (B) INPUT 0 0 0 0 0 3 4 s6
10 (24) (B) INPUT 0 0 0 0 0 3 4 s7
16 (19) (B) INPUT 0 0 0 0 0 0 4 s8
88 (94) (F) INPUT 0 0 0 0 0 0 4 s9
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