vga.map.rpt

用1K30DE FPGA写的程序

;       |addcore:adder|                  ; 8 (1)       ; 0            ; 0           ; 0    ; 8 (1)        ; 0 (0)             ; 0 (0)            ; 8 (1)           ; |vga|lpm_add_sub:add_rtl_2|addcore:adder                         ;
;          |a_csnbuffer:result_node|     ; 7 (7)       ; 0            ; 0           ; 0    ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 7 (7)           ; |vga|lpm_add_sub:add_rtl_2|addcore:adder|a_csnbuffer:result_node ;
;    |lpm_counter:cc_rtl_0|              ; 5 (0)       ; 5            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 5 (0)            ; 5 (0)           ; |vga|lpm_counter:cc_rtl_0                                        ;
;       |alt_counter_f10ke:wysi_counter| ; 5 (5)       ; 5            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 5 (5)            ; 5 (5)           ; |vga|lpm_counter:cc_rtl_0|alt_counter_f10ke:wysi_counter         ;
;    |lpm_counter:fs_rtl_1|              ; 3 (0)       ; 3            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 3 (0)            ; 3 (0)           ; |vga|lpm_counter:fs_rtl_1                                        ;
;       |alt_counter_f10ke:wysi_counter| ; 3 (3)       ; 3            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 3 (3)            ; 3 (3)           ; |vga|lpm_counter:fs_rtl_1|alt_counter_f10ke:wysi_counter         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA/JHEDA1K30/VGA/VGA.map.eqn.


+-------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                              ;
+-------------------------------------------------------------------+-----------------+
; File Name                                                         ; Used in Netlist ;
+-------------------------------------------------------------------+-----------------+
; VGA.VHD                                                           ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_constant.inc      ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/flex10ke_lcell.inc    ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/addcore.inc           ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/addcore.tdf           ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf       ; yes             ;
; d:/altera/quartus41/libraries/megafunctions/altshift.tdf          ; yes             ;
+-------------------------------------------------------------------+-----------------+


+----------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                  ;
+-----------------------------------+----------------------------------------------------------+
; Resource                          ; Usage                                                    ;
+-----------------------------------+----------------------------------------------------------+
; Logic cells                       ; 54                                                       ;
; Total combinational functions     ; 51                                                       ;
; Total 4-input functions           ; 25                                                       ;
; Total 3-input functions           ; 4                                                        ;
; Total 2-input functions           ; 5                                                        ;
; Total 1-input functions           ; 9                                                        ;
; Total 0-input functions           ; 8                                                        ;
; Combinational cells for routing   ; 0                                                        ;
; Total registers                   ; 19                                                       ;
; Total logic cells in carry chains ; 17                                                       ;
; I/O pins                          ; 7                                                        ;
; Maximum fan-out node              ; lpm_counter:cc_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ;
; Maximum fan-out                   ; 14                                                       ;
; Total fan-out                     ; 173                                                      ;
; Average fan-out                   ; 2.84                                                     ;
+-----------------------------------+----------------------------------------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 8     ;
; Number of synthesis-generated cells                    ; 46    ;
; Number of WYSIWYG LUTs                                 ; 8     ;
; Number of synthesis-generated LUTs                     ; 43    ;
; Number of WYSIWYG registers                            ; 8     ;
; Number of synthesis-generated registers                ; 11    ;
; Number of cells with combinational logic only          ; 35    ;
; Number of cells with registers only                    ; 3     ;
; Number of cells with combinational logic and registers ; 16    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue Dec 14 00:35:20 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off VGA -c VGA
Info: Found 2 design units, including 1 entities, in source file VGA.VHD
    Info: Found design unit 1: vga-behv
    Info: Found entity 1: vga
Warning: VHDL Process Statement warning at VGA.VHD(44): signal grbx is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at VGA.VHD(46): signal grby is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at VGA.VHD(48): signal grbx is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at VGA.VHD(48): signal grby is in statement, but is not in sensitivity list
Info: Inferred 2 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: cc[0]~0
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: fs[0]~0
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/alt_counter_f10ke.tdf
    Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Implemented 61 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 54 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue Dec 14 00:35:26 2004
    Info: Elapsed time: 00:00:06