vga.rpt

用1K30DE FPGA写的程序

!_LC8_B10 = _LC8_B10~NOT;
_LC8_B10~NOT = LCELL( _EQ027);
  _EQ027 = !cc3
         # !cc4;

-- Node name is ':873' 
-- Equation name is '_LC6_D23', type is buried 
!_LC6_D23 = _LC6_D23~NOT;
_LC6_D23~NOT = LCELL( _EQ028);
  _EQ028 = !_LC2_D24
         # !ll8
         # !ll7;

-- Node name is ':1100' 
-- Equation name is '_LC2_B18', type is buried 
_LC2_B18 = LCELL( _EQ029);
  _EQ029 = !cc2 & !cc3 & !cc4 & !_LC3_B18;

-- Node name is ':1127' 
-- Equation name is '_LC3_B10', type is buried 
!_LC3_B10 = _LC3_B10~NOT;
_LC3_B10~NOT = LCELL( _EQ030);
  _EQ030 =  cc3
         #  cc4
         #  cc1 &  cc2;

-- Node name is ':1154' 
-- Equation name is '_LC4_B4', type is buried 
_LC4_B4  = LCELL( _EQ031);
  _EQ031 = !cc2 & !cc4 &  _LC6_B18
         # !cc3 & !cc4;

-- Node name is ':1181' 
-- Equation name is '_LC6_B4', type is buried 
!_LC6_B4 = _LC6_B4~NOT;
_LC6_B4~NOT = LCELL( _EQ032);
  _EQ032 =  cc2 &  cc3
         #  cc4;

-- Node name is ':1233' 
-- Equation name is '_LC4_B10', type is buried 
!_LC4_B10 = _LC4_B10~NOT;
_LC4_B10~NOT = LCELL( _EQ033);
  _EQ033 =  cc2 &  cc4
         #  cc1 &  cc4
         #  cc3 &  cc4;

-- Node name is ':1272' 
-- Equation name is '_LC6_B18', type is buried 
_LC6_B18 = LCELL( _EQ034);
  _EQ034 = !cc0 & !cc1;

-- Node name is ':1375' 
-- Equation name is '_LC6_B16', type is buried 
_LC6_B16 = LCELL( _EQ035);
  _EQ035 = !_LC1_B4
         #  _LC2_B18
         #  _LC3_B10;

-- Node name is '~1398~1' 
-- Equation name is '~1398~1', location is LC1_B4, type is buried.
-- synthesized logic cell 
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL( _EQ036);
  _EQ036 = !cc3 & !cc4
         # !cc2 & !cc4
         #  _LC4_B4;

-- Node name is ':1399' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ037);
  _EQ037 =  _LC1_B4 &  _LC4_B10
         #  _LC2_B18
         #  _LC3_B10;

-- Node name is '~1423~1' 
-- Equation name is '~1423~1', location is LC5_B4, type is buried.
-- synthesized logic cell 
_LC5_B4  = LCELL( _EQ038);
  _EQ038 = !cc3 & !_LC4_B10 &  _LC6_B18
         # !cc2 & !cc3 & !_LC4_B10;

-- Node name is '~1423~2' 
-- Equation name is '~1423~2', location is LC8_B4, type is buried.
-- synthesized logic cell 
_LC8_B4  = LCELL( _EQ039);
  _EQ039 =  _LC5_B4 & !_LC6_B4
         # !cc4 & !_LC6_B4 & !_LC7_B4;

-- Node name is ':1423' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = LCELL( _EQ040);
  _EQ040 =  _LC2_B18
         # !_LC3_B10 &  _LC4_B4
         # !_LC3_B10 &  _LC8_B4;

-- Node name is '~1437~1' 
-- Equation name is '~1437~1', location is LC7_D24, type is buried.
-- synthesized logic cell 
!_LC7_D24 = _LC7_D24~NOT;
_LC7_D24~NOT = LCELL( _EQ041);
  _EQ041 =  ll8
         #  ll7;

-- Node name is ':1437' 
-- Equation name is '_LC4_D24', type is buried 
_LC4_D24 = LCELL( _EQ042);
  _EQ042 =  _LC6_D24 &  _LC7_D24 & !ll6;

-- Node name is ':1450' 
-- Equation name is '_LC6_D24', type is buried 
_LC6_D24 = LCELL( _EQ043);
  _EQ043 = !ll3
         # !ll2
         # !ll5
         # !ll4;

-- Node name is ':1488' 
-- Equation name is '_LC5_D24', type is buried 
!_LC5_D24 = _LC5_D24~NOT;
_LC5_D24~NOT = LCELL( _EQ044);
  _EQ044 = !_LC7_D24
         #  _LC2_D24 &  ll3 &  ll4;

-- Node name is ':1539' 
-- Equation name is '_LC3_D24', type is buried 
_LC3_D24 = LCELL( _EQ045);
  _EQ045 =  _LC8_D24 & !ll6 & !ll8
         # !ll7 & !ll8;

-- Node name is ':1552' 
-- Equation name is '_LC8_D24', type is buried 
_LC8_D24 = LCELL( _EQ046);
  _EQ046 = !ll2 & !ll3
         # !ll5
         # !ll4;

-- Node name is ':1590' 
-- Equation name is '_LC1_D23', type is buried 
!_LC1_D23 = _LC1_D23~NOT;
_LC1_D23~NOT = LCELL( _EQ047);
  _EQ047 =  _LC2_D24 &  ll4 &  ll7
         #  ll8;

-- Node name is '~1593~1' 
-- Equation name is '~1593~1', location is LC2_D24, type is buried.
-- synthesized logic cell 
!_LC2_D24 = _LC2_D24~NOT;
_LC2_D24~NOT = LCELL( _EQ048);
  _EQ048 = !ll5
         # !ll6;

-- Node name is ':1639' 
-- Equation name is '_LC1_D27', type is buried 
_LC1_D27 = LCELL( _EQ049);
  _EQ049 =  _LC2_D27 & !ll6 & !ll7
         # !ll8;

-- Node name is ':1654' 
-- Equation name is '_LC2_D27', type is buried 
_LC2_D27 = LCELL( _EQ050);
  _EQ050 = !ll3 & !ll4
         # !ll2 & !ll4
         # !ll5;

-- Node name is ':1692' 
-- Equation name is '_LC2_D23', type is buried 
!_LC2_D23 = _LC2_D23~NOT;
_LC2_D23~NOT = LCELL( _EQ051);
  _EQ051 =  _LC2_D24 &  ll4
         #  _LC2_D24 &  ll3
         #  ll7;

-- Node name is ':1746' 
-- Equation name is '_LC5_D22', type is buried 
_LC5_D22 = LCELL( _EQ052);
  _EQ052 = !ll5 & !ll6
         #  _LC4_D28 & !ll6
         # !ll7;

-- Node name is ':1758' 
-- Equation name is '_LC4_D28', type is buried 
!_LC4_D28 = _LC4_D28~NOT;
_LC4_D28~NOT = LCELL( _EQ053);
  _EQ053 =  ll4
         #  ll3
         #  ll2;

-- Node name is '~1876~1' 
-- Equation name is '~1876~1', location is LC1_D24, type is buried.
-- synthesized logic cell 
_LC1_D24 = LCELL( _EQ054);
  _EQ054 =  _LC6_D24 &  _LC7_D24 & !ll6
         #  _LC5_D24;

-- Node name is ':1876' 
-- Equation name is '_LC3_D23', type is buried 
_LC3_D23 = LCELL( _EQ055);
  _EQ055 = !_LC8_D23
         #  _LC1_D24;

-- Node name is '~1899~1' 
-- Equation name is '~1899~1', location is LC8_D23, type is buried.
-- synthesized logic cell 
!_LC8_D23 = _LC8_D23~NOT;
_LC8_D23~NOT = LCELL( _EQ056);
  _EQ056 =  _LC3_D24
         #  _LC1_D23;

-- Node name is ':1900' 
-- Equation name is '_LC5_D23', type is buried 
_LC5_D23 = LCELL( _EQ057);
  _EQ057 =  _LC1_D27 &  _LC8_D23
         #  _LC2_D23 &  _LC8_D23
         #  _LC1_D24;

-- Node name is ':1920' 
-- Equation name is '_LC4_D23', type is buried 
_LC4_D23 = LCELL( _EQ058);
  _EQ058 = !_LC1_D23 &  _LC1_D27
         # !_LC1_D23 & !_LC2_D23 &  _LC5_D22;

-- Node name is ':1924' 
-- Equation name is '_LC7_D23', type is buried 
_LC7_D23 = LCELL( _EQ059);
  _EQ059 =  _LC4_D24
         #  _LC3_D24 & !_LC5_D24
         #  _LC4_D23 & !_LC5_D24;

-- Node name is ':1966' 
-- Equation name is '_LC1_B10', type is buried 
_LC1_B10 = LCELL( _EQ060);
  _EQ060 =  _LC3_B16 & !_LC6_D23 & !_LC8_B10 & !md
         # !_LC3_B16 & !_LC6_D23 & !_LC8_B10 &  md;

-- Node name is ':1976' 
-- Equation name is '_LC6_B10', type is buried 
_LC6_B10 = LCELL( _EQ061);
  _EQ061 =  _LC2_B16 & !_LC6_D23 & !_LC8_B10 & !md
         # !_LC2_B16 & !_LC6_D23 & !_LC8_B10 &  md;

-- Node name is ':1986' 
-- Equation name is '_LC2_B10', type is buried 
_LC2_B10 = LCELL( _EQ062);
  _EQ062 =  _LC1_B16 & !_LC6_D23 & !_LC8_B10 & !md
         # !_LC1_B16 & !_LC6_D23 & !_LC8_B10 &  md;



Project Information                                   e:\jheda1k30\vga\vga.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = on
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   EDIF Netlist Writer                    00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 24,376K