infifo.v

千兆以太网控制器.可以调整FIFO,和传输速率,在码流层进行控制.

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// The synopsys directives "translate_off/translate_on" specified below are
// supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).

// You must compile the wrapper file infifo.v when simulating
// the core, infifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".

`timescale 1ns/1ps

module infifo(
	din,
	wr_en,
	wr_clk,
	rd_en,
	rd_clk,
	ainit,
	dout,
	full,
	empty);


input [7 : 0] din;
input wr_en;
input wr_clk;
input rd_en;
input rd_clk;
input ainit;
output [7 : 0] dout;
output full;
output empty;

// synopsys translate_off

      ASYNC_FIFO_V6_1 #(
		8,	// c_data_width
		0,	// c_enable_rlocs
		511,	// c_fifo_depth
		0,	// c_has_almost_empty
		0,	// c_has_almost_full
		0,	// c_has_rd_ack
		0,	// c_has_rd_count
		0,	// c_has_rd_err
		0,	// c_has_wr_ack
		0,	// c_has_wr_count
		0,	// c_has_wr_err
		0,	// c_rd_ack_low
		2,	// c_rd_count_width
		0,	// c_rd_err_low
		1,	// c_use_blockmem
		0,	// c_wr_ack_low
		2,	// c_wr_count_width
		0)	// c_wr_err_low
	inst (
		.DIN(din),
		.WR_EN(wr_en),
		.WR_CLK(wr_clk),
		.RD_EN(rd_en),
		.RD_CLK(rd_clk),
		.AINIT(ainit),
		.DOUT(dout),
		.FULL(full),
		.EMPTY(empty),
		.ALMOST_FULL(),
		.ALMOST_EMPTY(),
		.WR_COUNT(),
		.RD_COUNT(),
		.RD_ACK(),
		.RD_ERR(),
		.WR_ACK(),
		.WR_ERR());


// synopsys translate_on

// FPGA Express black box declaration
// synopsys attribute fpga_dont_touch "true"
// synthesis attribute fpga_dont_touch of infifo is "true"

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of infifo is "black_box"

endmodule