📄 ddcm.vhi
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-- VHDL Instantiation Created from source file ddcm.vhd -- 21:56:00 10/20/2006
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
COMPONENT ddcm
PORT(
CLKIN_IN : IN std_logic;
RST_IN : IN std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic;
CLK90_OUT : OUT std_logic;
CLK180_OUT : OUT std_logic;
CLK270_OUT : OUT std_logic;
LOCKED_OUT : OUT std_logic
);
END COMPONENT;
Inst_ddcm: ddcm PORT MAP(
CLKIN_IN => ,
RST_IN => ,
CLKIN_IBUFG_OUT => ,
CLK0_OUT => ,
CLK90_OUT => ,
CLK180_OUT => ,
CLK270_OUT => ,
LOCKED_OUT =>
);
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