📄 video_segmentation.rpt
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Total I/O pins used: 62/86 ( 72%)
Total logic cells used: 144/576 ( 25%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.01/4 ( 75%)
Total fan-in: 434/2304 ( 18%)
Total input pins required: 28
Total input I/O cell registers required: 0
Total output pins required: 40
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 144
Total flipflops required: 77
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 21/ 576 ( 3%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 1 0 0 1 1 0 0 0 0 0 1 0 8 8 1 1 8 0 0 8 6 0 0 1 45/0
B: 1 1 0 1 1 0 8 0 8 8 1 0 0 1 0 0 8 7 8 8 8 0 1 0 1 71/0
C: 0 0 1 1 1 0 0 8 8 0 2 1 0 0 1 0 1 1 0 1 0 0 1 1 0 28/0
Total: 1 2 1 2 3 1 8 8 16 8 3 2 0 9 9 1 10 16 8 9 16 6 2 1 2 144/0
Device-Specific Information: d:\cotrol\video_segmentation.rpt
video_segmentation
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - - -- INPUT ^ 0 0 0 1 BLUE0
125 - - - -- INPUT ^ 0 0 0 1 BLUE1
51 - - - 13 INPUT ^ 0 0 0 1 BLUE2
73 - - - 02 INPUT ^ 0 0 0 1 BLUE3
32 - - C -- INPUT ^ 0 0 0 1 BLUE4
135 - - - 18 INPUT ^ 0 0 0 1 BLUE5
23 - - B -- INPUT ^ 0 0 0 1 BLUE6
64 - - - 10 INPUT ^ 0 0 0 1 BLUE7
55 - - - -- INPUT G ^ 0 0 0 1 DCLK
124 - - - -- INPUT ^ 0 0 0 19 DE
83 - - C -- INPUT ^ 0 0 0 1 GREEN0
79 - - C -- INPUT ^ 0 0 0 1 GREEN1
78 - - C -- INPUT ^ 0 0 0 1 GREEN2
63 - - - 11 INPUT ^ 0 0 0 1 GREEN3
70 - - - 05 INPUT ^ 0 0 0 1 GREEN4
144 - - - 24 INPUT ^ 0 0 0 1 GREEN5
117 - - - 06 INPUT ^ 0 0 0 1 GREEN6
41 - - - 20 INPUT ^ 0 0 0 1 GREEN7
54 - - - -- INPUT G ^ 0 0 0 20 HS
133 - - - 17 INPUT ^ 0 0 0 1 RED0
98 - - A -- INPUT ^ 0 0 0 1 RED1
37 - - - 23 INPUT ^ 0 0 0 1 RED2
17 - - B -- INPUT ^ 0 0 0 1 RED3
90 - - B -- INPUT ^ 0 0 0 1 RED4
27 - - C -- INPUT ^ 0 0 0 1 RED5
92 - - B -- INPUT ^ 0 0 0 1 RED6
42 - - - 19 INPUT ^ 0 0 0 1 RED7
56 - - - -- INPUT G ^ 0 0 0 0 VS
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\cotrol\video_segmentation.rpt
video_segmentation
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
13 - - A -- OUTPUT 0 1 0 0 ADDRESS0
43 - - - 18 OUTPUT 0 1 0 0 ADDRESS1
8 - - A -- OUTPUT 0 1 0 0 ADDRESS2
11 - - A -- OUTPUT 0 1 0 0 ADDRESS3
130 - - - 14 OUTPUT 0 1 0 0 ADDRESS4
100 - - A -- OUTPUT 0 1 0 0 ADDRESS5
14 - - A -- OUTPUT 0 1 0 0 ADDRESS6
96 - - A -- OUTPUT 0 1 0 0 ADDRESS7
102 - - A -- OUTPUT 0 1 0 0 ADDRESS8
141 - - - 22 OUTPUT 0 1 0 0 ADDRESS9
140 - - - 21 OUTPUT 0 1 0 0 ADDRESS10
9 - - A -- OUTPUT 0 1 0 0 ADDRESS11
39 - - - 21 OUTPUT 0 1 0 0 ADDRESS12
109 - - - 01 OUTPUT 0 0 0 0 ADDRESS13
114 - - - 04 OUTPUT 0 1 0 0 DATA0
113 - - - 03 OUTPUT 0 1 0 0 DATA1
29 - - C -- OUTPUT 0 1 0 0 DATA2
88 - - B -- OUTPUT 0 1 0 0 DATA3
48 - - - 15 OUTPUT 0 1 0 0 DATA4
21 - - B -- OUTPUT 0 1 0 0 DATA5
91 - - B -- OUTPUT 0 1 0 0 DATA6
72 - - - 04 OUTPUT 0 1 0 0 DATA7
33 - - C -- OUTPUT 0 1 0 0 DATA8
81 - - C -- OUTPUT 0 1 0 0 DATA9
142 - - - 23 OUTPUT 0 1 0 0 DATA10
95 - - A -- OUTPUT 0 1 0 0 DATA11
80 - - C -- OUTPUT 0 1 0 0 DATA12
132 - - - 16 OUTPUT 0 1 0 0 DATA13
62 - - - 11 OUTPUT 0 1 0 0 DATA14
26 - - C -- OUTPUT 0 1 0 0 DATA15
47 - - - 16 OUTPUT 0 1 0 0 DATA16
97 - - A -- OUTPUT 0 1 0 0 DATA17
7 - - A -- OUTPUT 0 1 0 0 DATA18
87 - - B -- OUTPUT 0 1 0 0 DATA19
86 - - B -- OUTPUT 0 1 0 0 DATA20
30 - - C -- OUTPUT 0 1 0 0 DATA21
19 - - B -- OUTPUT 0 1 0 0 DATA22
18 - - B -- OUTPUT 0 1 0 0 DATA23
44 - - - 18 OUTPUT 0 0 0 0 OE
116 - - - 05 OUTPUT 0 1 0 0 WE
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\cotrol\video_segmentation.rpt
video_segmentation
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 09 OR2 s ! 1 3 0 2 DE~1
- 3 - B 19 AND2 0 2 0 1 |LPM_ADD_SUB:292|addcore:adder|:75
- 4 - B 19 AND2 0 4 0 4 |LPM_ADD_SUB:292|addcore:adder|:83
- 5 - B 18 AND2 0 2 0 1 |LPM_ADD_SUB:292|addcore:adder|:87
- 1 - B 18 AND2 0 4 0 2 |LPM_ADD_SUB:292|addcore:adder|:95
- 6 - C 09 AND2 0 3 0 3 |LPM_ADD_SUB:491|addcore:adder|:87
- 8 - C 09 AND2 0 3 0 3 |LPM_ADD_SUB:491|addcore:adder|:95
- 2 - C 09 AND2 0 3 0 3 |LPM_ADD_SUB:491|addcore:adder|:103
- 3 - C 08 AND2 0 3 0 2 |LPM_ADD_SUB:491|addcore:adder|:111
- 4 - B 10 AND2 0 2 0 1 |LPM_ADD_SUB:774|addcore:adder|:75
- 1 - B 10 AND2 0 3 0 2 |LPM_ADD_SUB:774|addcore:adder|:79
- 3 - B 10 AND2 0 2 0 2 |LPM_ADD_SUB:774|addcore:adder|:83
- 8 - B 10 AND2 0 2 0 2 |LPM_ADD_SUB:774|addcore:adder|:87
- 3 - B 07 AND2 0 2 0 2 |LPM_ADD_SUB:774|addcore:adder|:91
- 5 - B 07 AND2 0 2 0 2 |LPM_ADD_SUB:774|addcore:adder|:95
- 7 - B 07 AND2 0 2 0 1 |LPM_ADD_SUB:774|addcore:adder|:99
- 4 - B 17 AND2 0 3 0 1 |LPM_ADD_SUB:1310|addcore:adder|:79
- 2 - B 17 AND2 0 4 0 3 |LPM_ADD_SUB:1310|addcore:adder|:83
- 3 - B 16 AND2 0 3 0 2 |LPM_ADD_SUB:1310|addcore:adder|:91
- 5 - A 21 AND2 0 2 0 1 |LPM_ADD_SUB:1877|addcore:adder|:55
- 4 - A 17 AND2 0 3 0 7 |LPM_ADD_SUB:1976|addcore:adder|:79
- 5 - A 13 OR2 ! 0 2 0 1 |LPM_ADD_SUB:1976|addcore:adder|:83
- 5 - A 14 AND2 0 3 0 4 |LPM_ADD_SUB:1976|addcore:adder|:87
- 2 - A 20 AND2 0 2 0 1 |LPM_ADD_SUB:1976|addcore:adder|:91
- 7 - A 20 AND2 0 4 0 1 |LPM_ADD_SUB:1976|addcore:adder|:99
- 2 - B 22 DFFE + 1 0 1 0 :29
- 2 - B 24 DFFE + 1 0 1 0 :31
- 8 - C 14 DFFE + 1 0 1 0 :33
- 8 - B 05 DFFE + 1 0 1 0 :35
- 7 - B 11 DFFE + 1 0 1 0 :37
- 1 - A 24 DFFE + 1 0 1 0 :39
- 5 - A 02 DFFE + 1 0 1 0 :41
- 1 - A 16 DFFE + 1 0 1 0 :43
- 1 - C 22 DFFE + 1 0 1 0 :45
- 4 - A 12 DFFE + 1 0 1 0 :47
- 4 - A 15 DFFE + 1 0 1 0 :49
- 4 - C 05 DFFE + 1 0 1 0 :51
- 8 - A 05 DFFE + 1 0 1 0 :53
- 4 - C 23 DFFE + 1 0 1 0 :55
- 2 - C 12 DFFE + 1 0 1 0 :57
- 8 - C 17 DFFE + 1 0 1 0 :59
- 2 - B 04 DFFE + 1 0 1 0 :61
- 2 - B 02 DFFE + 1 0 1 0 :63
- 5 - B 13 DFFE + 1 0 1 0 :65
- 4 - C 16 DFFE + 1 0 1 0 :67
- 6 - B 01 DFFE + 1 0 1 0 :69
- 4 - C 19 DFFE + 1 0 1 0 :71
- 4 - C 03 DFFE + 1 0 1 0 :73
- 1 - C 04 DFFE + 1 0 1 0 :75
- 4 - B 18 DFFE + 0 3 0 1 HOLD_HS_COUNTER8 (:93)
- 2 - B 18 DFFE + 0 2 0 2 HOLD_HS_COUNTER7 (:94)
- 6 - B 18 DFFE + 0 3 0 2 HOLD_HS_COUNTER6 (:95)
- 7 - B 18 DFFE + 0 3 0 3 HOLD_HS_COUNTER5 (:96)
- 8 - B 18 DFFE + 0 2 0 4 HOLD_HS_COUNTER4 (:97)
- 5 - B 19 DFFE + 0 3 0 2 HOLD_HS_COUNTER3 (:98)
- 6 - B 19 DFFE + 0 3 0 3 HOLD_HS_COUNTER2 (:99)
- 7 - B 19 DFFE + 0 2 0 4 HOLD_HS_COUNTER1 (:100)
- 8 - B 19 DFFE + 0 1 0 5 HOLD_HS_COUNTER0 (:101)
- 6 - C 08 DFFE + 0 3 0 1 HS_COUNTER10 (:102)
- 4 - C 08 DFFE + 0 2 0 2 HS_COUNTER9 (:103)
- 2 - C 08 DFFE + 0 3 0 2 HS_COUNTER8 (:104)
- 5 - C 08 DFFE + 0 2 0 3 HS_COUNTER7 (:105)
- 4 - C 09 DFFE + 0 3 0 2 HS_COUNTER6 (:106)
- 3 - C 09 DFFE + 0 2 0 3 HS_COUNTER5 (:107)
- 1 - C 09 DFFE + 0 3 0 2 HS_COUNTER4 (:108)
- 7 - C 09 DFFE + 0 2 0 2 HS_COUNTER3 (:109)
- 5 - C 09 DFFE + 0 3 0 1 HS_COUNTER2 (:110)
- 4 - C 11 DFFE + 0 2 0 2 HS_COUNTER1 (:111)
- 1 - C 11 DFFE + 0 1 0 3 HS_COUNTER0 (:112)
- 8 - B 07 DFFE + 2 2 0 1 HOLD_PIXEL_COUNTER8 (:114)
- 6 - B 07 DFFE + 2 2 0 2 HOLD_PIXEL_COUNTER7 (:115)
- 4 - B 07 DFFE + 2 2 0 2 HOLD_PIXEL_COUNTER6 (:116)
- 1 - B 07 DFFE + 2 2 0 2 HOLD_PIXEL_COUNTER5 (:117)
- 7 - B 10 DFFE + 2 2 0 2 HOLD_PIXEL_COUNTER4 (:118)
- 6 - B 10 DFFE + 2 2 0 2 HOLD_PIXEL_COUNTER3 (:119)
- 5 - B 10 DFFE + 2 2 0 2 HOLD_PIXEL_COUNTER2 (:120)
- 7 - B 09 DFFE + 2 2 0 3 HOLD_PIXEL_COUNTER1 (:121)
- 2 - B 09 DFFE + 2 1 0 4 HOLD_PIXEL_COUNTER0 (:122)
- 6 - B 09 DFFE + 1 1 0 2 PIXEL_COUNTER10 (:123)
- 3 - B 09 DFFE + 1 2 0 2 PIXEL_COUNTER9 (:124)
- 8 - B 09 DFFE + 1 2 0 1 PIXEL_COUNTER8 (:125)
- 6 - B 16 DFFE + 2 2 0 2 PIXEL_COUNTER7 (:126)
- 8 - B 16 DFFE + 2 2 0 3 PIXEL_COUNTER6 (:127)
- 2 - B 16 DFFE + 2 2 0 3 PIXEL_COUNTER5 (:128)
- 8 - B 20 DFFE + 2 2 0 4 PIXEL_COUNTER4 (:129)
- 7 - B 17 DFFE + 2 2 0 3 PIXEL_COUNTER3 (:130)
- 3 - B 20 DFFE + 2 2 0 4 PIXEL_COUNTER2 (:131)
- 6 - B 20 DFFE + 2 2 0 5 PIXEL_COUNTER1 (:132)
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