📄 control.rpt
字号:
143 - - B -- OUTPUT 0 1 0 0 RDATA1
149 - - A -- OUTPUT 0 1 0 0 RDATA2
134 - - C -- OUTPUT 0 1 0 0 RDATA3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\jlh\cotrol\control.rpt
control
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - C 27 SOFT s r 0 1 1 0 A_OE~fit~in1
- 2 - F 28 DFFE +s 0 0 1 0 |DATA_ASSIGN:1|C~1 (|DATA_ASSIGN:1|~162~1)
- 4 - C 36 DFFE + 0 0 0 41 |DATA_ASSIGN:1|C (|DATA_ASSIGN:1|:162)
- 5 - C 26 OR2 0 3 1 0 |DATA_ASSIGN:1|:198
- 4 - C 25 OR2 0 3 1 0 |DATA_ASSIGN:1|:204
- 1 - C 26 OR2 0 3 1 0 |DATA_ASSIGN:1|:210
- 1 - C 27 OR2 0 3 1 0 |DATA_ASSIGN:1|:216
- 2 - C 27 OR2 0 3 1 0 |DATA_ASSIGN:1|:222
- 2 - C 29 OR2 0 3 1 0 |DATA_ASSIGN:1|:228
- 8 - C 29 OR2 0 3 1 0 |DATA_ASSIGN:1|:234
- 7 - C 31 OR2 0 3 1 0 |DATA_ASSIGN:1|:240
- 8 - C 32 OR2 0 3 1 0 |DATA_ASSIGN:1|:246
- 3 - C 33 OR2 0 3 1 0 |DATA_ASSIGN:1|:252
- 1 - C 34 OR2 0 3 1 0 |DATA_ASSIGN:1|:258
- 3 - C 36 OR2 0 3 1 0 |DATA_ASSIGN:1|:264
- 2 - C 36 OR2 0 3 1 0 |DATA_ASSIGN:1|:270
- 6 - C 26 OR2 0 3 1 0 |DATA_ASSIGN:1|:289
- 3 - C 27 OR2 0 3 1 0 |DATA_ASSIGN:1|:295
- 8 - C 27 OR2 0 3 1 0 |DATA_ASSIGN:1|:301
- 5 - C 27 OR2 0 3 1 0 |DATA_ASSIGN:1|:307
- 7 - C 29 OR2 0 3 1 0 |DATA_ASSIGN:1|:313
- 3 - C 29 OR2 0 3 1 0 |DATA_ASSIGN:1|:319
- 7 - C 32 OR2 0 3 1 0 |DATA_ASSIGN:1|:325
- 3 - C 31 OR2 0 3 1 0 |DATA_ASSIGN:1|:331
- 7 - C 34 OR2 0 3 1 0 |DATA_ASSIGN:1|:337
- 8 - C 33 OR2 0 3 1 0 |DATA_ASSIGN:1|:343
- 3 - C 34 OR2 0 3 1 0 |DATA_ASSIGN:1|:349
- 5 - C 36 OR2 0 3 1 0 |DATA_ASSIGN:1|:355
- 7 - C 36 OR2 0 3 1 0 |DATA_ASSIGN:1|:361
- 1 - C 31 OR2 1 2 1 0 |DATA_ASSIGN:1|:374
- 5 - C 31 OR2 1 2 1 0 |DATA_ASSIGN:1|:387
- 6 - C 36 OR2 0 3 0 1 |DATA_ASSIGN:1|:921
- 5 - D 10 OR2 0 3 0 1 |DATA_ASSIGN:1|:927
- 8 - D 10 OR2 0 3 0 1 |DATA_ASSIGN:1|:969
- 8 - C 36 OR2 0 3 0 1 |DATA_ASSIGN:1|:975
- 7 - D 16 OR2 0 3 0 1 |DATA_ASSIGN:1|:1017
- 5 - D 16 OR2 0 3 0 1 |DATA_ASSIGN:1|:1023
- 4 - C 32 AND2 0 2 0 1 |DATA_MANAGE:2|LPM_ADD_SUB:1119|addcore:adder|:63
- 6 - C 24 AND2 0 3 0 1 |DATA_MANAGE:2|LPM_ADD_SUB:1119|addcore:adder|:67
- 1 - C 24 AND2 0 4 0 2 |DATA_MANAGE:2|LPM_ADD_SUB:1119|addcore:adder|:71
- 3 - C 24 AND2 0 2 0 1 |DATA_MANAGE:2|LPM_ADD_SUB:1119|addcore:adder|:75
- 7 - D 14 AND2 0 3 0 2 |DATA_MANAGE:2|LPM_ADD_SUB:1288|addcore:adder|:63
- 5 - B 14 DFFE + 0 3 1 0 |DATA_MANAGE:2|:49
- 3 - B 14 DFFE + 0 3 1 0 |DATA_MANAGE:2|:51
- 3 - B 15 DFFE + 0 3 1 0 |DATA_MANAGE:2|:53
- 4 - B 14 DFFE + 0 3 1 0 |DATA_MANAGE:2|:55
- 8 - B 15 DFFE + 0 3 1 0 |DATA_MANAGE:2|:57
- 4 - B 15 DFFE + 0 3 1 0 |DATA_MANAGE:2|:59
- 6 - B 15 DFFE + 0 3 1 0 |DATA_MANAGE:2|:61
- 1 - B 15 DFFE + 0 3 1 0 |DATA_MANAGE:2|:63
- 1 - B 12 DFFE + 0 3 1 0 |DATA_MANAGE:2|:65
- 1 - A 14 DFFE + 0 3 1 0 |DATA_MANAGE:2|:67
- 8 - A 14 DFFE + 0 3 1 0 |DATA_MANAGE:2|:69
- 1 - D 16 DFFE + 0 3 1 0 |DATA_MANAGE:2|:71
- 1 - B 22 DFFE + 0 1 0 1 |DATA_MANAGE:2|CONTROL_B7 (|DATA_MANAGE:2|:73)
- 5 - B 22 DFFE + 0 1 0 2 |DATA_MANAGE:2|CONTROL_B6 (|DATA_MANAGE:2|:74)
- 4 - B 22 DFFE + 0 1 0 2 |DATA_MANAGE:2|CONTROL_B5 (|DATA_MANAGE:2|:75)
- 3 - B 22 DFFE + 0 1 0 2 |DATA_MANAGE:2|CONTROL_B4 (|DATA_MANAGE:2|:76)
- 2 - B 27 DFFE + 0 1 0 2 |DATA_MANAGE:2|CONTROL_B3 (|DATA_MANAGE:2|:77)
- 5 - B 27 DFFE + 0 1 0 2 |DATA_MANAGE:2|CONTROL_B2 (|DATA_MANAGE:2|:78)
- 4 - B 27 DFFE + 0 1 0 2 |DATA_MANAGE:2|CONTROL_B1 (|DATA_MANAGE:2|:79)
- 3 - B 27 DFFE + 1 0 0 2 |DATA_MANAGE:2|CONTROL_B0 (|DATA_MANAGE:2|:80)
- 2 - B 25 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T7 (|DATA_MANAGE:2|:81)
- 6 - B 22 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T6 (|DATA_MANAGE:2|:82)
- 7 - B 22 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T5 (|DATA_MANAGE:2|:83)
- 8 - B 22 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T4 (|DATA_MANAGE:2|:84)
- 1 - B 25 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T3 (|DATA_MANAGE:2|:85)
- 6 - B 27 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T2 (|DATA_MANAGE:2|:86)
- 7 - B 27 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T1 (|DATA_MANAGE:2|:87)
- 8 - B 27 DFFE 1 1 0 1 |DATA_MANAGE:2|CONTROL_T0 (|DATA_MANAGE:2|:88)
- 8 - C 12 DFFE + 0 2 0 3 |DATA_MANAGE:2|CLK_COUNTER2 (|DATA_MANAGE:2|:89)
- 7 - C 12 DFFE + 0 1 0 4 |DATA_MANAGE:2|CLK_COUNTER1 (|DATA_MANAGE:2|:90)
- 2 - C 04 DFFE + 0 0 0 5 |DATA_MANAGE:2|CLK_COUNTER0 (|DATA_MANAGE:2|:91)
- 2 - C 12 DFFE + 0 2 1 16 |DATA_MANAGE:2|CHUNNEL_COUNTER1 (|DATA_MANAGE:2|:92)
- 4 - C 12 DFFE + 0 1 0 6 |DATA_MANAGE:2|CHUNNEL_COUNTER0 (|DATA_MANAGE:2|:93)
- 2 - C 35 DFFE + 0 3 0 4 |DATA_MANAGE:2|SECT_COUNTER2 (|DATA_MANAGE:2|:95)
- 3 - C 35 DFFE + 0 2 0 5 |DATA_MANAGE:2|SECT_COUNTER1 (|DATA_MANAGE:2|:96)
- 7 - C 35 DFFE + 0 1 0 6 |DATA_MANAGE:2|SECT_COUNTER0 (|DATA_MANAGE:2|:97)
- 8 - C 35 DFFE + 0 2 0 4 |DATA_MANAGE:2|L_COUNTER1 (|DATA_MANAGE:2|:99)
- 6 - C 35 DFFE + 0 1 0 5 |DATA_MANAGE:2|L_COUNTER0 (|DATA_MANAGE:2|:100)
- 2 - C 24 DFFE + 0 3 0 5 |DATA_MANAGE:2|BLOCK_COUNTER5 (|DATA_MANAGE:2|:102)
- 7 - C 24 DFFE + 0 3 0 4 |DATA_MANAGE:2|BLOCK_COUNTER4 (|DATA_MANAGE:2|:103)
- 8 - C 24 DFFE + 0 3 0 4 |DATA_MANAGE:2|BLOCK_COUNTER3 (|DATA_MANAGE:2|:104)
- 1 - C 32 DFFE + 0 3 0 5 |DATA_MANAGE:2|BLOCK_COUNTER2 (|DATA_MANAGE:2|:105)
- 4 - C 24 DFFE + 0 3 0 6 |DATA_MANAGE:2|BLOCK_COUNTER1 (|DATA_MANAGE:2|:106)
- 2 - C 33 DFFE + 0 1 0 9 |DATA_MANAGE:2|BLOCK_COUNTER0 (|DATA_MANAGE:2|:107)
- 5 - D 14 DFFE + 0 3 0 3 |DATA_MANAGE:2|SCAN_COUNTER4 (|DATA_MANAGE:2|:109)
- 1 - D 14 DFFE + 0 2 0 4 |DATA_MANAGE:2|SCAN_COUNTER3 (|DATA_MANAGE:2|:110)
- 6 - D 14 DFFE + 0 3 0 4 |DATA_MANAGE:2|SCAN_COUNTER2 (|DATA_MANAGE:2|:111)
- 3 - D 14 DFFE + 0 2 0 6 |DATA_MANAGE:2|SCAN_COUNTER1 (|DATA_MANAGE:2|:112)
- 2 - D 14 DFFE + 0 1 0 4 |DATA_MANAGE:2|SCAN_COUNTER0 (|DATA_MANAGE:2|:113)
- 7 - B 14 DFFE + 0 2 0 1 |DATA_MANAGE:2|R_BIT3 (|DATA_MANAGE:2|:115)
- 2 - B 14 DFFE + 0 2 0 2 |DATA_MANAGE:2|R_BIT2 (|DATA_MANAGE:2|:116)
- 6 - B 14 DFFE + 0 2 0 2 |DATA_MANAGE:2|R_BIT1 (|DATA_MANAGE:2|:117)
- 1 - B 14 DFFE + 0 3 0 2 |DATA_MANAGE:2|R_BIT0 (|DATA_MANAGE:2|:118)
- 2 - A 14 DFFE + 0 2 0 1 |DATA_MANAGE:2|B_BIT3 (|DATA_MANAGE:2|:119)
- 4 - A 14 DFFE + 0 2 0 2 |DATA_MANAGE:2|B_BIT2 (|DATA_MANAGE:2|:120)
- 3 - A 14 DFFE + 0 2 0 2 |DATA_MANAGE:2|B_BIT1 (|DATA_MANAGE:2|:121)
- 4 - D 16 DFFE + 0 3 0 2 |DATA_MANAGE:2|B_BIT0 (|DATA_MANAGE:2|:122)
- 7 - B 15 DFFE + 0 2 0 1 |DATA_MANAGE:2|G_BIT3 (|DATA_MANAGE:2|:123)
- 5 - B 15 DFFE + 0 2 0 2 |DATA_MANAGE:2|G_BIT2 (|DATA_MANAGE:2|:124)
- 2 - B 15 DFFE + 0 2 0 2 |DATA_MANAGE:2|G_BIT1 (|DATA_MANAGE:2|:125)
- 8 - B 14 DFFE + 0 3 0 2 |DATA_MANAGE:2|G_BIT0 (|DATA_MANAGE:2|:126)
- 5 - C 33 OR2 s 0 4 0 5 |DATA_MANAGE:2|~1190~1
- 3 - C 12 OR2 ! 0 3 0 12 |DATA_MANAGE:2|:1410
- 1 - C 12 OR2 s ! 0 4 0 12 |DATA_MANAGE:2|~1974~1
- 5 - C 12 AND2 0 3 0 3 |DATA_MANAGE:2|:2204
- 6 - C 12 AND2 0 3 0 4 |DATA_MANAGE:2|:2226
- 1 - C 35 AND2 0 4 0 3 |DATA_MANAGE:2|:2246
- 5 - C 35 AND2 0 3 0 8 |DATA_MANAGE:2|:2265
- 4 - C 33 AND2 0 4 0 5 |DATA_MANAGE:2|:2288
- 2 - D 10 OR2 0 4 0 1 |DATA_MANAGE:2|:2340
- 3 - D 10 OR2 0 4 0 1 |DATA_MANAGE:2|:2341
- 1 - D 10 OR2 0 4 0 1 |DATA_MANAGE:2|:2345
- 1 - C 36 OR2 0 3 0 1 |DATA_MANAGE:2|:2351
- 8 - D 14 OR2 0 4 0 1 |DATA_MANAGE:2|:2399
- 6 - D 10 OR2 0 4 0 1 |DATA_MANAGE:2|:2400
- 7 - D 10 OR2 0 4 0 1 |DATA_MANAGE:2|:2404
- 4 - D 10 OR2 0 3 0 1 |DATA_MANAGE:2|:2410
- 2 - D 16 OR2 0 4 0 1 |DATA_MANAGE:2|:2458
- 4 - D 14 AND2 s 0 2 0 3 |DATA_MANAGE:2|~2459~1
- 3 - D 16 OR2 0 4 0 1 |DATA_MANAGE:2|:2459
- 6 - D 16 OR2 0 4 0 1 |DATA_MANAGE:2|:2463
- 8 - D 16 OR2 0 3 0 1 |DATA_MANAGE:2|:2469
- 5 - C 24 AND2 s 0 4 0 3 |DATA_MANAGE:2|~2507~1
- 4 - C 35 AND2 s 0 4 0 1 |DATA_MANAGE:2|~2507~2
- 6 - C 33 AND2 s 0 4 0 1 |DATA_MANAGE:2|~2507~3
- 1 - C 33 AND2 0 4 1 0 |DATA_MANAGE:2|:2507
- 1 - B 27 OR2 s 0 3 0 1 |DATA_MANAGE:2|~2521~1
- 2 - B 22 OR2 s 0 3 0 1 |DATA_MANAGE:2|~2521~2
- 5 - B 25 OR2 ! 0 4 1 0 |DATA_MANAGE:2|:2521
- 3 - F 21 AND2 s 1 1 0 8 DE~1
- 4 - A 13 AND2 0 2 0 1 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:292|addcore:adder|:75
- 1 - A 13 AND2 0 4 0 4 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:292|addcore:adder|:83
- 5 - A 16 AND2 0 2 0 1 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:292|addcore:adder|:87
- 1 - A 16 AND2 0 4 0 2 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:292|addcore:adder|:95
- 6 - F 33 AND2 0 3 0 3 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:491|addcore:adder|:87
- 8 - F 33 AND2 0 3 0 3 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:491|addcore:adder|:95
- 1 - F 33 AND2 0 3 0 3 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:491|addcore:adder|:103
- 3 - F 19 AND2 0 3 0 2 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:491|addcore:adder|:111
- 7 - F 31 AND2 0 2 0 1 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:774|addcore:adder|:75
- 1 - F 31 AND2 0 3 0 2 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:774|addcore:adder|:79
- 3 - F 31 AND2 0 2 0 2 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:774|addcore:adder|:83
- 5 - F 31 AND2 0 2 0 2 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:774|addcore:adder|:87
- 1 - F 26 AND2 0 2 0 2 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:774|addcore:adder|:91
- 3 - F 26 AND2 0 2 0 2 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:774|addcore:adder|:95
- 4 - F 26 AND2 0 2 0 1 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:774|addcore:adder|:99
- 4 - F 27 AND2 0 2 0 4 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:1045|addcore:adder|:83
- 7 - F 27 AND2 0 2 0 1 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:1045|addcore:adder|:87
- 1 - F 27 AND2 0 4 0 4 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:1045|addcore:adder|:95
- 5 - F 21 AND2 0 2 0 1 |VIDEO_SEGMENTATION:3|LPM_ADD_SUB:1045|addcore:adder|:99
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