📄 data_assign.rpt
字号:
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 24 DFFE + 0 0 0 56 C (:162)
- 6 - A 24 OR2 2 1 1 0 :192
- 1 - E 30 OR2 2 1 1 0 :198
- 1 - A 20 OR2 2 1 1 0 :204
- 6 - B 14 OR2 2 1 1 0 :210
- 5 - C 17 OR2 2 1 1 0 :216
- 2 - A 23 OR2 2 1 1 0 :222
- 8 - F 32 OR2 2 1 1 0 :228
- 6 - E 25 OR2 2 1 1 0 :234
- 1 - C 03 OR2 2 1 1 0 :240
- 2 - C 18 OR2 2 1 1 0 :246
- 4 - F 19 OR2 2 1 1 0 :252
- 1 - C 22 OR2 2 1 1 0 :258
- 2 - E 35 OR2 2 1 1 0 :264
- 5 - D 08 OR2 2 1 1 0 :270
- 1 - A 24 OR2 2 1 1 0 :283
- 5 - E 30 OR2 2 1 1 0 :289
- 2 - A 20 OR2 2 1 1 0 :295
- 4 - B 14 OR2 2 1 1 0 :301
- 3 - C 17 OR2 2 1 1 0 :307
- 4 - A 23 OR2 2 1 1 0 :313
- 6 - F 32 OR2 2 1 1 0 :319
- 5 - E 25 OR2 2 1 1 0 :325
- 2 - C 03 OR2 2 1 1 0 :331
- 6 - C 18 OR2 2 1 1 0 :337
- 1 - F 19 OR2 2 1 1 0 :343
- 4 - C 22 OR2 2 1 1 0 :349
- 4 - E 35 OR2 2 1 1 0 :355
- 2 - D 08 OR2 2 1 1 0 :361
- 1 - D 12 OR2 2 1 1 0 :374
- 2 - D 12 OR2 2 1 1 0 :387
- 8 - F 22 OR2 2 1 1 0 :400
- 3 - F 22 OR2 2 1 1 0 :413
- 6 - D 16 LCELL s 1 0 1 0 ~432~1
- 1 - F 02 LCELL s 1 0 1 0 ~442~1
- 2 - B 06 LCELL s 1 0 1 0 ~452~1
- 1 - B 13 LCELL s 1 0 1 0 ~462~1
- 5 - B 34 LCELL s 1 0 1 0 ~472~1
- 5 - D 19 LCELL s 1 0 1 0 ~482~1
- 1 - C 19 LCELL s 1 0 1 0 ~492~1
- 6 - C 29 LCELL s 1 0 1 0 ~502~1
- 6 - F 03 LCELL s 1 0 1 0 ~512~1
- 5 - A 04 LCELL s 1 0 1 0 ~522~1
- 6 - C 07 LCELL s 1 0 1 0 ~532~1
- 4 - E 08 LCELL s 1 0 1 0 ~542~1
- 2 - D 26 LCELL s 1 0 1 0 ~552~1
- 2 - F 08 LCELL s 1 0 1 0 ~562~1
- 4 - A 11 LCELL s 1 0 1 0 ~572~1
- 3 - E 29 LCELL s 1 0 1 0 ~582~1
- 6 - A 30 LCELL s 1 0 1 0 ~592~1
- 5 - F 01 LCELL s 1 0 1 0 ~602~1
- 6 - D 01 LCELL s 1 0 1 0 ~612~1
- 3 - C 31 LCELL s 1 0 1 0 ~622~1
- 1 - C 08 LCELL s 1 0 1 0 ~632~1
- 3 - B 27 LCELL s 1 0 1 0 ~642~1
- 4 - B 28 LCELL s 1 0 1 0 ~652~1
- 6 - D 24 LCELL s 1 0 1 0 ~662~1
- 1 - D 16 LCELL s 1 0 1 0 ~680~1
- 3 - F 02 LCELL s 1 0 1 0 ~690~1
- 6 - B 06 LCELL s 1 0 1 0 ~700~1
- 5 - B 13 LCELL s 1 0 1 0 ~710~1
- 2 - B 34 LCELL s 1 0 1 0 ~720~1
- 3 - D 19 LCELL s 1 0 1 0 ~730~1
- 4 - C 19 LCELL s 1 0 1 0 ~740~1
- 5 - C 29 LCELL s 1 0 1 0 ~750~1
- 1 - F 03 LCELL s 1 0 1 0 ~760~1
- 8 - A 04 LCELL s 1 0 1 0 ~770~1
- 5 - C 07 LCELL s 1 0 1 0 ~780~1
- 8 - E 08 LCELL s 1 0 1 0 ~790~1
- 3 - D 26 LCELL s 1 0 1 0 ~800~1
- 3 - F 08 LCELL s 1 0 1 0 ~810~1
- 3 - A 11 LCELL s 1 0 1 0 ~820~1
- 1 - E 29 LCELL s 1 0 1 0 ~830~1
- 8 - A 30 LCELL s 1 0 1 0 ~840~1
- 8 - F 01 LCELL s 1 0 1 0 ~850~1
- 3 - D 01 LCELL s 1 0 1 0 ~860~1
- 8 - C 31 LCELL s 1 0 1 0 ~870~1
- 4 - C 08 LCELL s 1 0 1 0 ~880~1
- 6 - B 27 LCELL s 1 0 1 0 ~890~1
- 6 - B 28 LCELL s 1 0 1 0 ~900~1
- 1 - D 24 LCELL s 1 0 1 0 ~910~1
- 4 - D 08 OR2 0 3 1 0 :921
- 2 - F 32 OR2 0 3 1 0 :927
- 1 - B 14 OR2 0 3 1 0 :933
- 2 - B 14 OR2 0 3 1 0 :939
- 8 - B 14 OR2 0 3 1 0 :945
- 3 - D 08 OR2 0 3 1 0 :951
- 7 - C 17 OR2 0 3 1 0 :957
- 4 - C 17 OR2 0 3 1 0 :963
- 3 - F 19 OR2 0 3 1 0 :969
- 3 - A 23 OR2 0 3 1 0 :975
- 8 - C 17 OR2 0 3 1 0 :981
- 2 - E 25 OR2 0 3 1 0 :987
- 1 - D 08 OR2 0 3 1 0 :993
- 1 - F 22 OR2 0 3 1 0 :999
- 5 - A 24 OR2 0 3 1 0 :1005
- 1 - E 25 OR2 0 3 1 0 :1011
- 5 - A 23 OR2 0 3 1 0 :1017
- 2 - F 22 OR2 0 3 1 0 :1023
- 8 - D 08 OR2 0 3 1 0 :1029
- 6 - C 17 OR2 0 3 1 0 :1035
- 1 - C 17 OR2 0 3 1 0 :1041
- 3 - B 14 OR2 0 3 1 0 :1047
- 5 - B 14 OR2 0 3 1 0 :1053
- 7 - D 08 OR2 0 3 1 0 :1059
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 11/144( 7%) 6/ 72( 8%) 8/ 72( 11%) 3/16( 18%) 3/16( 18%) 6/16( 37%)
B: 12/144( 8%) 9/ 72( 12%) 6/ 72( 8%) 0/16( 0%) 1/16( 6%) 10/16( 62%)
C: 17/144( 11%) 11/ 72( 15%) 6/ 72( 8%) 0/16( 0%) 3/16( 18%) 9/16( 56%)
D: 13/144( 9%) 10/ 72( 13%) 8/ 72( 11%) 0/16( 0%) 2/16( 12%) 10/16( 62%)
E: 7/144( 4%) 3/ 72( 4%) 10/ 72( 13%) 2/16( 12%) 3/16( 18%) 4/16( 25%)
F: 12/144( 8%) 9/ 72( 12%) 10/ 72( 13%) 0/16( 0%) 4/16( 25%) 8/16( 50%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
06: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
07: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
08: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
11: 3/24( 12%) 3/4( 75%) 0/4( 0%) 0/4( 0%)
12: 4/24( 16%) 2/4( 50%) 2/4( 50%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
14: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
15: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
17: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
18: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
19: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
20: 4/24( 16%) 1/4( 25%) 3/4( 75%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
22: 3/24( 12%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
23: 4/24( 16%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
25: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
26: 4/24( 16%) 2/4( 50%) 2/4( 50%) 0/4( 0%)
27: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 4/24( 16%) 2/4( 50%) 0/4( 0%) 1/4( 25%)
30: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
31: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
32: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
33: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
34: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
35: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
36: 3/24( 12%) 2/4( 50%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 1 VS
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** EQUATIONS **
DATA_ADDR0 : INPUT;
DATA_ADDR1 : INPUT;
DATA_ADDR2 : INPUT;
DATA_ADDR3 : INPUT;
DATA_ADDR4 : INPUT;
DATA_ADDR5 : INPUT;
DATA_ADDR6 : INPUT;
DATA_ADDR7 : INPUT;
DATA_ADDR8 : INPUT;
DATA_ADDR9 : INPUT;
DATA_ADDR10 : INPUT;
DATA_ADDR11 : INPUT;
DATA_ADDR12 : INPUT;
DATA_ADDR13 : INPUT;
DATA_OE : INPUT;
DATA_WE : INPUT;
VIDEO_ADDR0 : INPUT;
VIDEO_ADDR1 : INPUT;
VIDEO_ADDR2 : INPUT;
VIDEO_ADDR3 : INPUT;
VIDEO_ADDR4 : INPUT;
VIDEO_ADDR5 : INPUT;
VIDEO_ADDR6 : INPUT;
VIDEO_ADDR7 : INPUT;
VIDEO_ADDR8 : INPUT;
VIDEO_ADDR9 : INPUT;
VIDEO_ADDR10 : INPUT;
VIDEO_ADDR11 : INPUT;
VIDEO_ADDR12 : INPUT;
VIDEO_ADDR13 : INPUT;
VIDEO_DATA0 : INPUT;
VIDEO_DATA1 : INPUT;
VIDEO_DATA2 : INPUT;
VIDEO_DATA3 : INPUT;
VIDEO_DATA4 : INPUT;
VIDEO_DATA5 : INPUT;
VIDEO_DATA6 : INPUT;
VIDEO_DATA7 : INPUT;
VIDEO_DATA8 : INPUT;
VIDEO_DATA9 : INPUT;
VIDEO_DATA10 : INPUT;
VIDEO_DATA11 : INPUT;
VIDEO_DATA12 : INPUT;
VIDEO_DATA13 : INPUT;
VIDEO_DATA14 : INPUT;
VIDEO_DATA15 : INPUT;
VIDEO_DATA16 : INPUT;
VIDEO_DATA17 : INPUT;
VIDEO_DATA18 : INPUT;
VIDEO_DATA19 : INPUT;
VIDEO_DATA20 : INPUT;
VIDEO_DATA21 : INPUT;
VIDEO_DATA22 : INPUT;
VIDEO_DATA23 : INPUT;
VIDEO_OE : INPUT;
VIDEO_WE : INPUT;
VS : INPUT;
-- Node name is 'ADDR0'
-- Equation name is 'ADDR0', type is output
ADDR0 = _LC5_D8;
-- Node name is 'ADDR1'
-- Equation name is 'ADDR1', type is output
ADDR1 = _LC2_E35;
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