📄 data_assign.rpt
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Total single-pin Output Enables required: 0
Synthesized logic cells: 48/1728 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 2 0 0 4 4 0 0 0 0 0 2 0 0 0 0 0 0 16/0
B: 0 0 0 0 0 2 0 0 0 0 0 0 2 7 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 0 0 0 0 0 2 0 0 17/0
C: 0 0 2 0 0 0 2 2 0 0 0 0 0 0 0 0 7 2 0 2 0 0 2 0 0 0 0 0 0 2 0 2 0 0 0 0 0 23/0
D: 2 0 0 0 0 0 0 7 0 0 0 2 0 0 0 2 0 0 0 2 0 0 0 0 2 0 2 0 0 0 0 0 0 0 0 0 0 19/0
E: 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 2 2 0 0 0 0 2 0 12/0
F: 2 2 2 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 3 0 0 4 0 0 0 0 0 0 0 0 0 3 0 0 0 0 18/0
Total: 4 2 4 2 0 2 2 13 0 0 2 2 2 7 0 2 7 2 0 7 2 0 6 4 6 4 2 2 2 4 4 2 3 0 2 2 0 105/0
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
H15 - - D -- BIDIR ^ 0 1 0 1 B_DATA0
F15 - - B -- BIDIR ^ 0 1 0 1 B_DATA1
F16 - - B -- BIDIR ^ 0 1 0 1 B_DATA2
H4 - - C -- BIDIR ^ 0 1 0 1 B_DATA3
J5 - - C -- BIDIR ^ 0 1 0 1 B_DATA4
J3 - - D -- BIDIR ^ 0 1 0 1 B_DATA5
P2 - - F -- BIDIR ^ 0 1 0 1 B_DATA6
D15 - - A -- BIDIR ^ 0 1 0 1 B_DATA7
K2 - - E -- BIDIR ^ 0 1 0 1 B_DATA8
D2 - - A -- BIDIR ^ 0 1 0 1 B_DATA9
N2 - - F -- BIDIR ^ 0 1 0 1 B_DATA10
J14 - - D -- BIDIR ^ 0 1 0 1 B_DATA11
M2 - - E -- BIDIR ^ 0 1 0 1 B_DATA12
H3 - - C -- BIDIR ^ 0 1 0 1 B_DATA13
E1 - - A -- BIDIR ^ 0 1 0 1 B_DATA14
M1 - - F -- BIDIR ^ 0 1 0 1 B_DATA15
P14 - - - 29 BIDIR ^ 0 1 0 1 B_DATA16
G16 - - C -- BIDIR ^ 0 1 0 1 B_DATA17
J13 - - D -- BIDIR ^ 0 1 0 1 B_DATA18
F14 - - B -- BIDIR ^ 0 1 0 1 B_DATA19
F2 - - B -- BIDIR ^ 0 1 0 1 B_DATA20
G4 - - B -- BIDIR ^ 0 1 0 1 B_DATA21
M4 - - F -- BIDIR ^ 0 1 0 1 B_DATA22
J4 - - D -- BIDIR ^ 0 1 0 1 B_DATA23
T4 - - - 06 INPUT ^ 0 0 0 2 DATA_ADDR0
N10 - - - 23 INPUT ^ 0 0 0 2 DATA_ADDR1
R15 - - - 36 INPUT ^ 0 0 0 2 DATA_ADDR2
A13 - - - 30 INPUT ^ 0 0 0 2 DATA_ADDR3
C5 - - - 09 INPUT ^ 0 0 0 2 DATA_ADDR4
B4 - - - 04 INPUT ^ 0 0 0 2 DATA_ADDR5
L13 - - E -- INPUT ^ 0 0 0 2 DATA_ADDR6
R13 - - - 32 INPUT ^ 0 0 0 2 DATA_ADDR7
C1 - - A -- INPUT ^ 0 0 0 2 DATA_ADDR8
D7 - - - 15 INPUT ^ 0 0 0 2 DATA_ADDR9
D4 - - - 06 INPUT ^ 0 0 0 2 DATA_ADDR10
B13 - - - 31 INPUT ^ 0 0 0 2 DATA_ADDR11
A16 - - - 36 INPUT ^ 0 0 0 2 DATA_ADDR12
R9 - - - 19 INPUT ^ 0 0 0 2 DATA_ADDR13
T15 - - - 35 INPUT ^ 0 0 0 2 DATA_OE
E4 - - - 11 INPUT ^ 0 0 0 2 DATA_WE
K12 - - D -- BIDIR ^ 0 1 0 1 DATA0
F1 - - B -- BIDIR ^ 0 1 0 1 DATA1
G12 - - B -- BIDIR ^ 0 1 0 1 DATA2
G1 - - C -- BIDIR ^ 0 1 0 1 DATA3
G15 - - C -- BIDIR ^ 0 1 0 1 DATA4
J15 - - D -- BIDIR ^ 0 1 0 1 DATA5
N3 - - F -- BIDIR ^ 0 1 0 1 DATA6
E15 - - A -- BIDIR ^ 0 1 0 1 DATA7
K13 - - E -- BIDIR ^ 0 1 0 1 DATA8
D3 - - A -- BIDIR ^ 0 1 0 1 DATA9
M3 - - F -- BIDIR ^ 0 1 0 1 DATA10
J12 - - D -- BIDIR ^ 0 1 0 1 DATA11
L3 - - E -- BIDIR ^ 0 1 0 1 DATA12
H2 - - C -- BIDIR ^ 0 1 0 1 DATA13
F4 - - A -- BIDIR ^ 0 1 0 1 DATA14
N1 - - F -- BIDIR ^ 0 1 0 1 DATA15
H13 - - C -- BIDIR ^ 0 1 0 1 DATA16
G14 - - C -- BIDIR ^ 0 1 0 1 DATA17
J16 - - D -- BIDIR ^ 0 1 0 1 DATA18
G13 - - B -- BIDIR ^ 0 1 0 1 DATA19
E2 - - B -- BIDIR ^ 0 1 0 1 DATA20
G5 - - B -- BIDIR ^ 0 1 0 1 DATA21
M15 - - F -- BIDIR ^ 0 1 0 1 DATA22
K4 - - D -- BIDIR ^ 0 1 0 1 DATA23
T1 - - - 01 INPUT ^ 0 0 0 2 VIDEO_ADDR0
R12 - - - 27 INPUT ^ 0 0 0 2 VIDEO_ADDR1
N11 - - - 26 INPUT ^ 0 0 0 2 VIDEO_ADDR2
C14 - - - 33 INPUT ^ 0 0 0 2 VIDEO_ADDR3
D5 - - - 10 INPUT ^ 0 0 0 2 VIDEO_ADDR4
M8 - - - 16 INPUT ^ 0 0 0 2 VIDEO_ADDR5
T12 - - - 29 INPUT ^ 0 0 0 2 VIDEO_ADDR6
T14 - - - 34 INPUT ^ 0 0 0 2 VIDEO_ADDR7
F3 - - A -- INPUT ^ 0 0 0 2 VIDEO_ADDR8
T6 - - - 12 INPUT ^ 0 0 0 2 VIDEO_ADDR9
N6 - - - 10 INPUT ^ 0 0 0 2 VIDEO_ADDR10
E13 - - A -- INPUT ^ 0 0 0 2 VIDEO_ADDR11
K15 - - E -- INPUT ^ 0 0 0 2 VIDEO_ADDR12
B11 - - - 25 INPUT ^ 0 0 0 2 VIDEO_ADDR13
B9 - - - -- INPUT ^ 0 0 0 2 VIDEO_DATA0
E8 - - - -- INPUT ^ 0 0 0 2 VIDEO_DATA1
M9 - - - -- INPUT ^ 0 0 0 2 VIDEO_DATA2
R8 - - - -- INPUT ^ 0 0 0 2 VIDEO_DATA3
L8 - - - -- INPUT ^ 0 0 0 2 VIDEO_DATA4
A4 - - - 05 INPUT ^ 0 0 0 2 VIDEO_DATA5
R6 - - - 12 INPUT ^ 0 0 0 2 VIDEO_DATA6
D9 - - - 20 INPUT ^ 0 0 0 2 VIDEO_DATA7
D14 - - - 32 INPUT ^ 0 0 0 2 VIDEO_DATA8
A2 - - - 02 INPUT ^ 0 0 0 2 VIDEO_DATA9
T3 - - - 02 INPUT ^ 0 0 0 2 VIDEO_DATA10
R14 - - - 33 INPUT ^ 0 0 0 2 VIDEO_DATA11
R7 - - - 15 INPUT ^ 0 0 0 2 VIDEO_DATA12
B6 - - - 11 INPUT ^ 0 0 0 2 VIDEO_DATA13
P4 - - - 05 INPUT ^ 0 0 0 2 VIDEO_DATA14
C4 - - - 06 INPUT ^ 0 0 0 2 VIDEO_DATA15
C13 - - - 29 INPUT ^ 0 0 0 2 VIDEO_DATA16
R11 - - - 25 INPUT ^ 0 0 0 2 VIDEO_DATA17
P11 - - - 26 INPUT ^ 0 0 0 2 VIDEO_DATA18
A15 - - - 35 INPUT ^ 0 0 0 2 VIDEO_DATA19
R5 - - - 10 INPUT ^ 0 0 0 2 VIDEO_DATA20
C3 - - - 03 INPUT ^ 0 0 0 2 VIDEO_DATA21
P6 - - - 11 INPUT ^ 0 0 0 2 VIDEO_DATA22
E7 - - - 16 INPUT ^ 0 0 0 2 VIDEO_DATA23
C9 - - - 19 INPUT ^ 0 0 0 2 VIDEO_OE
T2 - - - 02 INPUT ^ 0 0 0 2 VIDEO_WE
A9 - - - -- INPUT G ^ 0 0 0 0 VS
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
R4 - - - 07 OUTPUT 0 1 0 0 ADDR0
P16 - - - 36 OUTPUT 0 1 0 0 ADDR1
C10 - - - 22 OUTPUT 0 1 0 0 ADDR2
N13 - - F -- OUTPUT 0 1 0 0 ADDR3
H12 - - C -- OUTPUT 0 1 0 0 ADDR4
P3 - - - 03 OUTPUT 0 1 0 0 ADDR5
D11 - - - 26 OUTPUT 0 1 0 0 ADDR6
N14 - - F -- OUTPUT 0 1 0 0 ADDR7
M10 - - - 24 OUTPUT 0 1 0 0 ADDR8
C8 - - - 18 OUTPUT 0 1 0 0 ADDR9
D6 - - - 13 OUTPUT 0 1 0 0 ADDR10
N9 - - - 20 OUTPUT 0 1 0 0 ADDR11
P13 - - - 30 OUTPUT 0 1 0 0 ADDR12
A11 - - - 24 OUTPUT 0 1 0 0 ADDR13
N5 - - - 07 OUTPUT 0 1 0 0 B_ADDR0
L14 - - E -- OUTPUT 0 1 0 0 B_ADDR1
A10 - - - 21 OUTPUT 0 1 0 0 B_ADDR2
P9 - - - 20 OUTPUT 0 1 0 0 B_ADDR3
B8 - - - 17 OUTPUT 0 1 0 0 B_ADDR4
R3 - - - 04 OUTPUT 0 1 0 0 B_ADDR5
L15 - - E -- OUTPUT 0 1 0 0 B_ADDR6
N16 - - F -- OUTPUT 0 1 0 0 B_ADDR7
D16 - - A -- OUTPUT 0 1 0 0 B_ADDR8
G2 - - C -- OUTPUT 0 1 0 0 B_ADDR9
A7 - - - 14 OUTPUT 0 1 0 0 B_ADDR10
E9 - - - 20 OUTPUT 0 1 0 0 B_ADDR11
L16 - - E -- OUTPUT 0 1 0 0 B_ADDR12
E10 - - - 23 OUTPUT 0 1 0 0 B_ADDR13
H15 - - D -- TRI 0 1 0 1 B_DATA0
F15 - - B -- TRI 0 1 0 1 B_DATA1
F16 - - B -- TRI 0 1 0 1 B_DATA2
H4 - - C -- TRI 0 1 0 1 B_DATA3
J5 - - C -- TRI 0 1 0 1 B_DATA4
J3 - - D -- TRI 0 1 0 1 B_DATA5
P2 - - F -- TRI 0 1 0 1 B_DATA6
D15 - - A -- TRI 0 1 0 1 B_DATA7
K2 - - E -- TRI 0 1 0 1 B_DATA8
D2 - - A -- TRI 0 1 0 1 B_DATA9
N2 - - F -- TRI 0 1 0 1 B_DATA10
J14 - - D -- TRI 0 1 0 1 B_DATA11
M2 - - E -- TRI 0 1 0 1 B_DATA12
H3 - - C -- TRI 0 1 0 1 B_DATA13
E1 - - A -- TRI 0 1 0 1 B_DATA14
M1 - - F -- TRI 0 1 0 1 B_DATA15
P14 - - - 29 TRI 0 1 0 1 B_DATA16
G16 - - C -- TRI 0 1 0 1 B_DATA17
J13 - - D -- TRI 0 1 0 1 B_DATA18
F14 - - B -- TRI 0 1 0 1 B_DATA19
F2 - - B -- TRI 0 1 0 1 B_DATA20
G4 - - B -- TRI 0 1 0 1 B_DATA21
M4 - - F -- TRI 0 1 0 1 B_DATA22
J4 - - D -- TRI 0 1 0 1 B_DATA23
T10 - - - 22 OUTPUT 0 1 0 0 B_OE
C6 - - - 12 OUTPUT 0 1 0 0 B_WE
K1 - - D -- OUTPUT 0 1 0 0 DATA_DATA0
N7 - - - 13 OUTPUT 0 1 0 0 DATA_DATA1
P7 - - - 14 OUTPUT 0 1 0 0 DATA_DATA2
N8 - - - 17 OUTPUT 0 1 0 0 DATA_DATA3
A8 - - - 17 OUTPUT 0 1 0 0 DATA_DATA4
J2 - - D -- OUTPUT 0 1 0 0 DATA_DATA5
M13 - - F -- OUTPUT 0 1 0 0 DATA_DATA6
D10 - - - 23 OUTPUT 0 1 0 0 DATA_DATA7
T11 - - - 25 OUTPUT 0 1 0 0 DATA_DATA8
F13 - - A -- OUTPUT 0 1 0 0 DATA_DATA9
R10 - - - 21 OUTPUT 0 1 0 0 DATA_DATA10
P5 - - - 08 OUTPUT 0 1 0 0 DATA_DATA11
C11 - - - 26 OUTPUT 0 1 0 0 DATA_DATA12
P8 - - - 18 OUTPUT 0 1 0 0 DATA_DATA13
E14 - - A -- OUTPUT 0 1 0 0 DATA_DATA14
T9 - - - 19 OUTPUT 0 1 0 0 DATA_DATA15
D8 - - - 18 OUTPUT 0 1 0 0 DATA_DATA16
H14 - - C -- OUTPUT 0 1 0 0 DATA_DATA17
B5 - - - 07 OUTPUT 0 1 0 0 DATA_DATA18
H5 - - B -- OUTPUT 0 1 0 0 DATA_DATA19
M7 - - - 13 OUTPUT 0 1 0 0 DATA_DATA20
B7 - - - 14 OUTPUT 0 1 0 0 DATA_DATA21
T13 - - - 31 OUTPUT 0 1 0 0 DATA_DATA22
A5 - - - 08 OUTPUT 0 1 0 0 DATA_DATA23
K12 - - D -- TRI 0 1 0 1 DATA0
F1 - - B -- TRI 0 1 0 1 DATA1
G12 - - B -- TRI 0 1 0 1 DATA2
G1 - - C -- TRI 0 1 0 1 DATA3
G15 - - C -- TRI 0 1 0 1 DATA4
J15 - - D -- TRI 0 1 0 1 DATA5
N3 - - F -- TRI 0 1 0 1 DATA6
E15 - - A -- TRI 0 1 0 1 DATA7
K13 - - E -- TRI 0 1 0 1 DATA8
D3 - - A -- TRI 0 1 0 1 DATA9
M3 - - F -- TRI 0 1 0 1 DATA10
J12 - - D -- TRI 0 1 0 1 DATA11
L3 - - E -- TRI 0 1 0 1 DATA12
H2 - - C -- TRI 0 1 0 1 DATA13
F4 - - A -- TRI 0 1 0 1 DATA14
N1 - - F -- TRI 0 1 0 1 DATA15
H13 - - C -- TRI 0 1 0 1 DATA16
G14 - - C -- TRI 0 1 0 1 DATA17
J16 - - D -- TRI 0 1 0 1 DATA18
G13 - - B -- TRI 0 1 0 1 DATA19
E2 - - B -- TRI 0 1 0 1 DATA20
G5 - - B -- TRI 0 1 0 1 DATA21
M15 - - F -- TRI 0 1 0 1 DATA22
K4 - - D -- TRI 0 1 0 1 DATA23
B10 - - - 22 OUTPUT 0 1 0 0 OE
A6 - - - 12 OUTPUT 0 1 0 0 WE
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
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