📄 data_assign.rpt
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Project Information d:\cotrol\data_assign.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 09/15/2004 14:47:08
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
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limited to modification, reverse engineering, de-compiling, or use with
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a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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***** Project compilation was successful
DATA_ASSIGN
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
data_assign
EP1K30FC256-1 57 56 48 0 0 % 105 6 %
User Pins: 57 56 48
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
***** Logic for device 'data_assign' compiled without errors.
Device: EP1K30FC256-1
ACEX 1K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
Enable Lock Output = OFF
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** ERROR SUMMARY **
Info: Chip 'data_assign' in device 'EP1K30FC256-1' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
----------------------------------------------------
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 |
|T o o o o o o o o o o o o o o o o T|
|R o o o o o o o o o o o o o o o o R|
|P o o o o o o o o o o o o o o o o P|
|N o o o o o o o o o o o o o o o o N|
|M o o o o o o o o o o o o o o o o M|
|L o o o o o o o o o o o o o o o o L|
|K o o o o o o o o o o o o o o o o K|
|J o o o o o o o o o o o o o o o o J|
|H o o o o o o o o o o o o o o o o H|
|G o o o o o o o o o o o o o o o o G|
|F o o o o o o o o o o o o o o o o F|
|E o o o o o o o o o o o o o o o o E|
|D o o o o o o o o o o o o o o o o D|
|C o o o o o o o o o o o o o o o o C|
|B o o o o o o o o o o o o o o o o B|
|A o o o o o o o o o o o o o o o o A|
| 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 |
----------------------------------------------------
EP1K30FC256-1
Bottom View
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
A1 ^DATA0 E1 B_DATA14 J1 N.C. N1 DATA15
A2 VIDEO_DATA9 E2 DATA20 J2 DATA_DATA5 N2 B_DATA10
A3 GND E3 N.C. J3 B_DATA5 N3 DATA6
A4 VIDEO_DATA5 E4 DATA_WE J4 B_DATA23 N4 ^nCONFIG
A5 DATA_DATA23 E5 GND J5 B_DATA4 N5 B_ADDR0
A6 WE E6 VCCIO J6 VCCIO N6 VIDEO_ADDR10
A7 B_ADDR10 E7 VIDEO_DATA23 J7 VCCINT N7 DATA_DATA1
A8 DATA_DATA4 E8 VIDEO_DATA1 J8 GND N8 DATA_DATA3
A9 VS E9 B_ADDR11 J9 GND N9 ADDR11
A10 B_ADDR2 E10 B_ADDR13 J10 VCCINT N10 DATA_ADDR1
A11 ADDR13 E11 VCCINT J11 VCCINT N11 VIDEO_ADDR2
A12 RESERVED E12 GND J12 DATA11 N12 VCCIO
A13 DATA_ADDR3 E13 VIDEO_ADDR11 J13 B_DATA18 N13 ADDR3
A14 GND E14 DATA_DATA14 J14 B_DATA11 N14 ADDR7
A15 VIDEO_DATA19 E15 DATA7 J15 DATA5 N15 N.C.
A16 DATA_ADDR12 E16 N.C. J16 DATA18 N16 B_ADDR7
B1 ^nCE F1 DATA1 K1 DATA_DATA0 P1 ^MSEL0
B2 ^DCLK F2 B_DATA20 K2 B_DATA8 P2 B_DATA6
B3 RESERVED F3 VIDEO_ADDR8 K3 N.C. P3 ADDR5
B4 DATA_ADDR5 F4 DATA14 K4 DATA23 P4 VIDEO_DATA14
B5 DATA_DATA18 F5 VCCINT K5 GND P5 DATA_DATA11
B6 VIDEO_DATA13 F6 GND K6 VCCIO P6 VIDEO_DATA22
B7 DATA_DATA21 F7 VCCINT K7 GND P7 DATA_DATA2
B8 B_ADDR4 F8 VCCIO K8 VCCIO P8 DATA_DATA13
B9 VIDEO_DATA0 F9 VCCINT K9 VCCINT P9 B_ADDR3
B10 OE F10 VCCIO K10 GND P10 RESERVED
B11 VIDEO_ADDR13 F11 GND K11 VCCIO P11 VIDEO_DATA18
B12 RESERVED F12 VCCINT K12 DATA0 P12 RESERVED
B13 DATA_ADDR11 F13 DATA_DATA9 K13 DATA8 P13 ADDR12
B14 RESERVED F14 B_DATA19 K14 N.C. P14 B_DATA16
B15 #TCK F15 B_DATA1 K15 VIDEO_ADDR12 P15 #TMS
B16 ^nCEO F16 B_DATA2 K16 N.C. P16 ADDR1
C1 DATA_ADDR8 G1 DATA3 L1 GND R1 ^MSEL1
C2 #TDI G2 B_ADDR9 L2 N.C. R2 VCCINT
C3 VIDEO_DATA21 G3 N.C. L3 DATA12 R3 B_ADDR5
C4 VIDEO_DATA15 G4 B_DATA21 L4 N.C. R4 ADDR0
C5 DATA_ADDR4 G5 DATA21 L5 VCCINT R5 VIDEO_DATA20
C6 B_WE G6 VCCIO L6 GND R6 VIDEO_DATA6
C7 GND G7 GND L7 VCCINT R7 VIDEO_DATA12
C8 ADDR9 G8 VCCIO L8 VIDEO_DATA4 R8 VIDEO_DATA3
C9 VIDEO_OE G9 GND L9 VCC_CKLK R9 DATA_ADDR13
C10 ADDR2 G10 GND L10 VCCIO R10 DATA_DATA10
C11 DATA_DATA12 G11 VCCIO L11 GND R11 VIDEO_DATA17
C12 RESERVED G12 DATA2 L12 VCCINT R12 VIDEO_ADDR1
C13 VIDEO_DATA16 G13 DATA19 L13 DATA_ADDR6 R13 DATA_ADDR7
C14 VIDEO_ADDR3 G14 DATA17 L14 B_ADDR1 R14 VIDEO_DATA11
C15 ^CONF_DONE G15 DATA4 L15 B_ADDR6 R15 DATA_ADDR2
C16 #TDO G16 B_DATA17 L16 B_ADDR12 R16 #TRST
D1 N.C. H1 N.C. M1 B_DATA15 T1 VIDEO_ADDR0
D2 B_DATA9 H2 DATA13 M2 B_DATA12 T2 VIDEO_WE
D3 DATA9 H3 B_DATA13 M3 DATA10 T3 VIDEO_DATA10
D4 DATA_ADDR10 H4 B_DATA3 M4 B_DATA22 T4 DATA_ADDR0
D5 VIDEO_ADDR4 H5 DATA_DATA19 M5 GND T5 RESERVED
D6 ADDR10 H6 VCCINT M6 VCCIO T6 VIDEO_ADDR9
D7 DATA_ADDR9 H7 VCCINT M7 DATA_DATA20 T7 RESERVED
D8 DATA_DATA16 H8 GND M8 VIDEO_ADDR5 T8 GND_CKLK
D9 VIDEO_DATA7 H9 GND M9 VIDEO_DATA2 T9 DATA_DATA15
D10 DATA_DATA7 H10 VCCINT M10 ADDR8 T10 B_OE
D11 ADDR6 H11 VCCIO M11 VCCINT T11 DATA_DATA8
D12 VCCIO H12 ADDR4 M12 GND T12 VIDEO_ADDR6
D13 RESERVED H13 DATA16 M13 DATA_DATA6 T13 DATA_DATA22
D14 VIDEO_DATA8 H14 DATA_DATA17 M14 N.C. T14 VIDEO_ADDR7
D15 B_DATA7 H15 B_DATA0 M15 DATA22 T15 DATA_OE
D16 B_ADDR8 H16 N.C. M16 N.C. T16 ^nSTATUS
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: d:\cotrol\data_assign.rpt
data_assign
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A4 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
A11 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
A20 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
A23 4/ 8( 50%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
A24 4/ 8( 50%) 3/ 8( 37%) 2/ 8( 25%) 1/2 0/2 4/22( 18%)
A30 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B6 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B14 7/ 8( 87%) 6/ 8( 75%) 1/ 8( 12%) 0/2 0/2 13/22( 59%)
B27 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B28 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
B34 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
C3 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C7 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
C8 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
C17 7/ 8( 87%) 5/ 8( 62%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
C18 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
C19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
C22 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
C29 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
C31 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
D1 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
D8 7/ 8( 87%) 5/ 8( 62%) 2/ 8( 25%) 0/2 0/2 13/22( 59%)
D12 2/ 8( 25%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 3/22( 13%)
D16 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
D19 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
D24 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
D26 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
E8 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
E25 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
E29 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
E30 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E35 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
F1 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
F2 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
F3 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
F8 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 1/22( 4%)
F19 3/ 8( 37%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 5/22( 22%)
F22 4/ 8( 50%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 7/22( 31%)
F32 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 5/22( 22%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 155/165 ( 93%)
Total logic cells used: 105/1728 ( 6%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.06/4 ( 51%)
Total fan-in: 217/6912 ( 3%)
Total input pins required: 57
Total input I/O cell registers required: 0
Total output pins required: 56
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 48
Total reserved pins required 0
Total logic cells required: 105
Total flipflops required: 1
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
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