📄 data_manage.rpt
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-- Node name is ':49'
-- Equation name is '_LC7_A23', type is buried
_LC7_A23 = DFFE( _EQ039, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ039 = !CHUNNEL_COUNTER1 & _LC2_A4 & R_BIT3
# CHUNNEL_COUNTER1 & _LC7_A23
# !_LC2_A4 & _LC7_A23;
-- Node name is ':51'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = DFFE( _EQ040, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ040 = !CHUNNEL_COUNTER1 & _LC2_A4 & R_BIT2
# CHUNNEL_COUNTER1 & _LC1_A18
# _LC1_A18 & !_LC2_A4;
-- Node name is ':53'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = DFFE( _EQ041, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ041 = !CHUNNEL_COUNTER1 & _LC2_A4 & R_BIT1
# CHUNNEL_COUNTER1 & _LC5_A6
# !_LC2_A4 & _LC5_A6;
-- Node name is ':55'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = DFFE( _EQ042, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ042 = !CHUNNEL_COUNTER1 & _LC2_A4 & R_BIT0
# CHUNNEL_COUNTER1 & _LC1_A6
# _LC1_A6 & !_LC2_A4;
-- Node name is ':57'
-- Equation name is '_LC2_A18', type is buried
_LC2_A18 = DFFE( _EQ043, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ043 = !CHUNNEL_COUNTER1 & G_BIT3 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC2_A18
# !_LC2_A4 & _LC2_A18;
-- Node name is ':59'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = DFFE( _EQ044, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ044 = !CHUNNEL_COUNTER1 & G_BIT2 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC5_A18
# !_LC2_A4 & _LC5_A18;
-- Node name is ':61'
-- Equation name is '_LC7_A18', type is buried
_LC7_A18 = DFFE( _EQ045, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ045 = !CHUNNEL_COUNTER1 & G_BIT1 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC7_A18
# !_LC2_A4 & _LC7_A18;
-- Node name is ':63'
-- Equation name is '_LC5_A12', type is buried
_LC5_A12 = DFFE( _EQ046, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ046 = !CHUNNEL_COUNTER1 & G_BIT0 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC5_A12
# !_LC2_A4 & _LC5_A12;
-- Node name is ':65'
-- Equation name is '_LC3_A23', type is buried
_LC3_A23 = DFFE( _EQ047, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ047 = B_BIT3 & !CHUNNEL_COUNTER1 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC3_A23
# !_LC2_A4 & _LC3_A23;
-- Node name is ':67'
-- Equation name is '_LC8_A23', type is buried
_LC8_A23 = DFFE( _EQ048, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ048 = B_BIT2 & !CHUNNEL_COUNTER1 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC8_A23
# !_LC2_A4 & _LC8_A23;
-- Node name is ':69'
-- Equation name is '_LC1_A23', type is buried
_LC1_A23 = DFFE( _EQ049, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ049 = B_BIT1 & !CHUNNEL_COUNTER1 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC1_A23
# _LC1_A23 & !_LC2_A4;
-- Node name is ':71'
-- Equation name is '_LC3_A3', type is buried
_LC3_A3 = DFFE( _EQ050, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ050 = B_BIT0 & !CHUNNEL_COUNTER1 & _LC2_A4
# CHUNNEL_COUNTER1 & _LC3_A3
# !_LC2_A4 & _LC3_A3;
-- Node name is '~1190~1'
-- Equation name is '~1190~1', location is LC2_B9, type is buried.
-- synthesized logic cell
_LC2_B9 = LCELL( _EQ051);
_EQ051 = !BLOCK_COUNTER5 & _LC1_B9
# !BLOCK_COUNTER0 & _LC1_B9
# _LC1_B9 & !_LC8_B7;
-- Node name is ':1410'
-- Equation name is '_LC3_A4', type is buried
!_LC3_A4 = _LC3_A4~NOT;
_LC3_A4~NOT = LCELL( _EQ052);
_EQ052 = !CLK_COUNTER2
# CLK_COUNTER1
# CLK_COUNTER0;
-- Node name is '~1974~1'
-- Equation name is '~1974~1', location is LC2_A4, type is buried.
-- synthesized logic cell
!_LC2_A4 = _LC2_A4~NOT;
_LC2_A4~NOT = LCELL( _EQ053);
_EQ053 = CHUNNEL_COUNTER0
# CLK_COUNTER1
# !CLK_COUNTER0
# CLK_COUNTER2;
-- Node name is ':2204'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ054);
_EQ054 = CLK_COUNTER0 & CLK_COUNTER1 & CLK_COUNTER2;
-- Node name is ':2226'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ055);
_EQ055 = CHUNNEL_COUNTER0 & CHUNNEL_COUNTER1 & _LC1_A4;
-- Node name is ':2246'
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = LCELL( _EQ056);
_EQ056 = _LC2_B1 & SECT_COUNTER0 & SECT_COUNTER1 & SECT_COUNTER2;
-- Node name is ':2265'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ057);
_EQ057 = L_COUNTER0 & L_COUNTER1 & _LC3_B6;
-- Node name is ':2288'
-- Equation name is '_LC5_A8', type is buried
_LC5_A8 = LCELL( _EQ058);
_EQ058 = BLOCK_COUNTER0 & BLOCK_COUNTER5 & _LC1_B9 & _LC8_B7;
-- Node name is ':2339'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = LCELL( _EQ059);
_EQ059 = DATA21 & SCAN_COUNTER1
# DATA20 & SCAN_COUNTER0 & !SCAN_COUNTER1;
-- Node name is ':2345'
-- Equation name is '_LC3_A6', type is buried
_LC3_A6 = LCELL( _EQ060);
_EQ060 = _LC2_A6 & !SCAN_COUNTER2
# DATA22 & SCAN_COUNTER2;
-- Node name is ':2351'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = LCELL( _EQ061);
_EQ061 = _LC3_A6 & !SCAN_COUNTER3
# DATA23 & SCAN_COUNTER3;
-- Node name is ':2398'
-- Equation name is '_LC1_A12', type is buried
_LC1_A12 = LCELL( _EQ062);
_EQ062 = DATA13 & SCAN_COUNTER1
# DATA12 & SCAN_COUNTER0 & !SCAN_COUNTER1;
-- Node name is ':2404'
-- Equation name is '_LC3_A12', type is buried
_LC3_A12 = LCELL( _EQ063);
_EQ063 = _LC1_A12 & !SCAN_COUNTER2
# DATA14 & SCAN_COUNTER2;
-- Node name is ':2410'
-- Equation name is '_LC4_A12', type is buried
_LC4_A12 = LCELL( _EQ064);
_EQ064 = _LC3_A12 & !SCAN_COUNTER3
# DATA15 & SCAN_COUNTER3;
-- Node name is ':2457'
-- Equation name is '_LC2_A8', type is buried
_LC2_A8 = LCELL( _EQ065);
_EQ065 = DATA5 & SCAN_COUNTER1
# DATA4 & SCAN_COUNTER0 & !SCAN_COUNTER1;
-- Node name is ':2463'
-- Equation name is '_LC1_A3', type is buried
_LC1_A3 = LCELL( _EQ066);
_EQ066 = _LC2_A8 & !SCAN_COUNTER2
# DATA6 & SCAN_COUNTER2;
-- Node name is ':2469'
-- Equation name is '_LC2_A3', type is buried
_LC2_A3 = LCELL( _EQ067);
_EQ067 = _LC1_A3 & !SCAN_COUNTER3
# DATA7 & SCAN_COUNTER3;
-- Node name is '~2507~1'
-- Equation name is '~2507~1', location is LC8_B7, type is buried.
-- synthesized logic cell
_LC8_B7 = LCELL( _EQ068);
_EQ068 = !BLOCK_COUNTER1 & !BLOCK_COUNTER2 & !BLOCK_COUNTER3 &
!BLOCK_COUNTER4;
-- Node name is '~2507~2'
-- Equation name is '~2507~2', location is LC5_B9, type is buried.
-- synthesized logic cell
_LC5_B9 = LCELL( _EQ069);
_EQ069 = !BLOCK_COUNTER5 & CHUNNEL_COUNTER0 & !L_COUNTER0 & !L_COUNTER1;
-- Node name is '~2507~3'
-- Equation name is '~2507~3', location is LC2_B6, type is buried.
-- synthesized logic cell
_LC2_B6 = LCELL( _EQ070);
_EQ070 = !BLOCK_COUNTER0 & SECT_COUNTER0 & !SECT_COUNTER1 & !SECT_COUNTER2;
-- Node name is ':2507'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ071);
_EQ071 = !CHUNNEL_COUNTER1 & _LC2_B6 & _LC5_B9 & _LC8_B7;
-- Node name is '~2521~1'
-- Equation name is '~2521~1', location is LC2_C13, type is buried.
-- synthesized logic cell
_LC2_C13 = LCELL( _EQ072);
_EQ072 = CONTROL_T2
# CONTROL_T1
# CONTROL_T0;
-- Node name is '~2521~2'
-- Equation name is '~2521~2', location is LC1_C20, type is buried.
-- synthesized logic cell
_LC1_C20 = LCELL( _EQ073);
_EQ073 = CONTROL_T6
# CONTROL_T5
# CONTROL_T4;
-- Node name is ':2521'
-- Equation name is '_LC2_C22', type is buried
!_LC2_C22 = _LC2_C22~NOT;
_LC2_C22~NOT = LCELL( _EQ074);
_EQ074 = CONTROL_T3
# _LC2_C13
# CONTROL_T7
# _LC1_C20;
Project Information d:\cotrol\data_manage.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,621K
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