📄 data_manage.rpt
字号:
20 - - C -- OUTPUT 0 1 0 0 EN
43 - - - 12 OUTPUT 0 1 0 0 GDATA0
10 - - A -- OUTPUT 0 1 0 0 GDATA1
8 - - A -- OUTPUT 0 1 0 0 GDATA2
6 - - A -- OUTPUT 0 1 0 0 GDATA3
65 - - B -- OUTPUT 0 1 0 0 LATCH_OUT
55 - - C -- OUTPUT 0 0 0 0 OE
71 - - A -- OUTPUT 0 1 0 0 RDATA0
69 - - A -- OUTPUT 0 1 0 0 RDATA1
5 - - A -- OUTPUT 0 1 0 0 RDATA2
9 - - A -- OUTPUT 0 1 0 0 RDATA3
58 - - C -- OUTPUT 0 0 0 0 WE
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\cotrol\data_manage.rpt
data_manage
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - B 07 AND2 0 2 0 4 |LPM_ADD_SUB:1119|addcore:adder|:63
- 5 - B 07 AND2 0 2 0 1 |LPM_ADD_SUB:1119|addcore:adder|:67
- 6 - B 07 AND2 0 3 0 1 |LPM_ADD_SUB:1119|addcore:adder|:71
- 3 - B 07 AND2 0 4 0 1 |LPM_ADD_SUB:1119|addcore:adder|:75
- 7 - A 08 AND2 0 3 0 2 |LPM_ADD_SUB:1288|addcore:adder|:63
- 7 - A 23 DFFE + 0 3 1 0 :49
- 1 - A 18 DFFE + 0 3 1 0 :51
- 5 - A 06 DFFE + 0 3 1 0 :53
- 1 - A 06 DFFE + 0 3 1 0 :55
- 2 - A 18 DFFE + 0 3 1 0 :57
- 5 - A 18 DFFE + 0 3 1 0 :59
- 7 - A 18 DFFE + 0 3 1 0 :61
- 5 - A 12 DFFE + 0 3 1 0 :63
- 3 - A 23 DFFE + 0 3 1 0 :65
- 8 - A 23 DFFE + 0 3 1 0 :67
- 1 - A 23 DFFE + 0 3 1 0 :69
- 3 - A 03 DFFE + 0 3 1 0 :71
- 2 - C 20 DFFE + 0 1 0 1 CONTROL_B7 (:73)
- 5 - C 20 DFFE + 0 1 0 2 CONTROL_B6 (:74)
- 4 - C 20 DFFE + 0 1 0 2 CONTROL_B5 (:75)
- 3 - C 20 DFFE + 0 1 0 2 CONTROL_B4 (:76)
- 1 - C 22 DFFE + 0 1 0 2 CONTROL_B3 (:77)
- 1 - C 13 DFFE + 0 1 0 2 CONTROL_B2 (:78)
- 4 - C 13 DFFE + 0 1 0 2 CONTROL_B1 (:79)
- 3 - C 13 DFFE + 1 0 0 2 CONTROL_B0 (:80)
- 4 - C 22 DFFE + 0 1 0 1 CONTROL_T7 (:81)
- 6 - C 20 DFFE + 0 1 0 1 CONTROL_T6 (:82)
- 7 - C 20 DFFE + 0 1 0 1 CONTROL_T5 (:83)
- 8 - C 20 DFFE + 0 1 0 1 CONTROL_T4 (:84)
- 3 - C 22 DFFE + 0 1 0 1 CONTROL_T3 (:85)
- 5 - C 13 DFFE + 0 1 0 1 CONTROL_T2 (:86)
- 6 - C 13 DFFE + 0 1 0 1 CONTROL_T1 (:87)
- 7 - C 13 DFFE + 0 1 0 1 CONTROL_T0 (:88)
- 6 - A 04 DFFE + 0 2 0 3 CLK_COUNTER2 (:89)
- 5 - A 04 DFFE + 0 1 0 4 CLK_COUNTER1 (:90)
- 4 - A 04 DFFE + 0 0 0 5 CLK_COUNTER0 (:91)
- 6 - B 01 DFFE +s 0 2 1 0 CHUNNEL_COUNTER1~1 (~92~1)
- 8 - B 01 DFFE + 0 2 1 14 CHUNNEL_COUNTER1 (:92)
- 1 - B 01 DFFE + 0 1 1 5 CHUNNEL_COUNTER0 (:93)
- 6 - B 06 DFFE + 0 3 1 2 SECT_COUNTER2 (:95)
- 5 - B 06 DFFE + 0 2 1 3 SECT_COUNTER1 (:96)
- 8 - B 06 DFFE + 0 1 1 4 SECT_COUNTER0 (:97)
- 8 - B 09 DFFE + 0 2 1 2 L_COUNTER1 (:99)
- 4 - B 09 DFFE + 0 1 1 3 L_COUNTER0 (:100)
- 7 - B 09 DFFE + 0 3 1 3 BLOCK_COUNTER5 (:102)
- 2 - B 07 DFFE + 0 3 1 2 BLOCK_COUNTER4 (:103)
- 7 - B 07 DFFE + 0 3 1 3 BLOCK_COUNTER3 (:104)
- 1 - B 07 DFFE + 0 3 1 4 BLOCK_COUNTER2 (:105)
- 3 - B 09 DFFE + 0 3 1 2 BLOCK_COUNTER1 (:106)
- 6 - B 09 DFFE + 0 1 1 5 BLOCK_COUNTER0 (:107)
- 3 - A 08 DFFE + 0 3 0 3 SCAN_COUNTER4 (:109)
- 8 - A 08 DFFE + 0 2 0 4 SCAN_COUNTER3 (:110)
- 6 - A 08 DFFE + 0 3 0 4 SCAN_COUNTER2 (:111)
- 4 - A 08 DFFE + 0 2 0 5 SCAN_COUNTER1 (:112)
- 1 - A 08 DFFE + 0 1 0 6 SCAN_COUNTER0 (:113)
- 6 - A 23 DFFE + 0 2 0 1 R_BIT3 (:115)
- 6 - A 06 DFFE + 0 2 0 2 R_BIT2 (:116)
- 8 - A 06 DFFE + 0 2 0 2 R_BIT1 (:117)
- 7 - A 06 DFFE + 0 3 0 2 R_BIT0 (:118)
- 5 - A 23 DFFE + 0 2 0 1 B_BIT3 (:119)
- 4 - A 23 DFFE + 0 2 0 2 B_BIT2 (:120)
- 2 - A 23 DFFE + 0 2 0 2 B_BIT1 (:121)
- 8 - A 03 DFFE + 0 3 0 2 B_BIT0 (:122)
- 6 - A 18 DFFE + 0 2 0 1 G_BIT3 (:123)
- 4 - A 18 DFFE + 0 2 0 2 G_BIT2 (:124)
- 3 - A 18 DFFE + 0 2 0 2 G_BIT1 (:125)
- 2 - A 12 DFFE + 0 3 0 2 G_BIT0 (:126)
- 2 - B 09 OR2 s 0 4 0 5 ~1190~1
- 3 - A 04 OR2 ! 0 3 0 12 :1410
- 2 - A 04 OR2 s ! 0 4 0 12 ~1974~1
- 1 - A 04 AND2 0 3 0 4 :2204
- 2 - B 01 AND2 0 3 0 4 :2226
- 3 - B 06 AND2 0 4 0 3 :2246
- 1 - B 09 AND2 0 3 0 8 :2265
- 5 - A 08 AND2 0 4 0 5 :2288
- 2 - A 06 OR2 2 2 0 1 :2339
- 3 - A 06 OR2 1 2 0 1 :2345
- 4 - A 06 OR2 1 2 0 1 :2351
- 1 - A 12 OR2 2 2 0 1 :2398
- 3 - A 12 OR2 1 2 0 1 :2404
- 4 - A 12 OR2 1 2 0 1 :2410
- 2 - A 08 OR2 2 2 0 1 :2457
- 1 - A 03 OR2 1 2 0 1 :2463
- 2 - A 03 OR2 1 2 0 1 :2469
- 8 - B 07 AND2 s 0 4 0 3 ~2507~1
- 5 - B 09 AND2 s 0 4 0 1 ~2507~2
- 2 - B 06 AND2 s 0 4 0 1 ~2507~3
- 1 - B 06 AND2 0 4 1 0 :2507
- 2 - C 13 OR2 s 0 3 0 1 ~2521~1
- 1 - C 20 OR2 s 0 3 0 1 ~2521~2
- 2 - C 22 OR2 ! 0 4 1 0 :2521
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: d:\cotrol\data_manage.rpt
data_manage
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 19/ 96( 19%) 11/ 48( 22%) 6/ 48( 12%) 1/16( 6%) 9/16( 56%) 0/16( 0%)
B: 11/ 96( 11%) 9/ 48( 18%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 4/ 96( 4%) 0/ 48( 0%) 3/ 48( 6%) 1/16( 6%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
02: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\cotrol\data_manage.rpt
data_manage
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 46 CLK50M
INPUT 8 MCU_CLK
INPUT 8 MCU_LATCH
Device-Specific Information: d:\cotrol\data_manage.rpt
data_manage
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 19 VS
Device-Specific Information: d:\cotrol\data_manage.rpt
data_manage
** EQUATIONS **
CLK50M : INPUT;
DATA4 : INPUT;
DATA5 : INPUT;
DATA6 : INPUT;
DATA7 : INPUT;
DATA12 : INPUT;
DATA13 : INPUT;
DATA14 : INPUT;
DATA15 : INPUT;
DATA20 : INPUT;
DATA21 : INPUT;
DATA22 : INPUT;
DATA23 : INPUT;
MCU_CLK : INPUT;
MCU_DATA : INPUT;
MCU_LATCH : INPUT;
VS : INPUT;
-- Node name is 'ADDR0'
-- Equation name is 'ADDR0', type is output
ADDR0 = SECT_COUNTER0;
-- Node name is 'ADDR1'
-- Equation name is 'ADDR1', type is output
ADDR1 = SECT_COUNTER1;
-- Node name is 'ADDR2'
-- Equation name is 'ADDR2', type is output
ADDR2 = SECT_COUNTER2;
-- Node name is 'ADDR3'
-- Equation name is 'ADDR3', type is output
ADDR3 = BLOCK_COUNTER0;
-- Node name is 'ADDR4'
-- Equation name is 'ADDR4', type is output
ADDR4 = BLOCK_COUNTER1;
-- Node name is 'ADDR5'
-- Equation name is 'ADDR5', type is output
ADDR5 = BLOCK_COUNTER2;
-- Node name is 'ADDR6'
-- Equation name is 'ADDR6', type is output
ADDR6 = BLOCK_COUNTER3;
-- Node name is 'ADDR7'
-- Equation name is 'ADDR7', type is output
ADDR7 = BLOCK_COUNTER4;
-- Node name is 'ADDR8'
-- Equation name is 'ADDR8', type is output
ADDR8 = BLOCK_COUNTER5;
-- Node name is 'ADDR9'
-- Equation name is 'ADDR9', type is output
ADDR9 = !L_COUNTER0;
-- Node name is 'ADDR10'
-- Equation name is 'ADDR10', type is output
ADDR10 = !L_COUNTER1;
-- Node name is 'ADDR11'
-- Equation name is 'ADDR11', type is output
ADDR11 = CHUNNEL_COUNTER0;
-- Node name is 'ADDR12'
-- Equation name is 'ADDR12', type is output
ADDR12 = _LC6_B1;
-- Node name is 'ADDR13'
-- Equation name is 'ADDR13', type is output
ADDR13 = GND;
-- Node name is ':122' = 'B_BIT0'
-- Equation name is 'B_BIT0', location is LC8_A3, type is buried.
B_BIT0 = DFFE( _EQ001, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ001 = _LC2_A3 & _LC3_A4 & !SCAN_COUNTER4
# B_BIT0 & !_LC3_A4;
-- Node name is ':121' = 'B_BIT1'
-- Equation name is 'B_BIT1', location is LC2_A23, type is buried.
B_BIT1 = DFFE( _EQ002, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ002 = B_BIT1 & !_LC3_A4
# B_BIT0 & _LC3_A4;
-- Node name is ':120' = 'B_BIT2'
-- Equation name is 'B_BIT2', location is LC4_A23, type is buried.
B_BIT2 = DFFE( _EQ003, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ003 = B_BIT2 & !_LC3_A4
# B_BIT1 & _LC3_A4;
-- Node name is ':119' = 'B_BIT3'
-- Equation name is 'B_BIT3', location is LC5_A23, type is buried.
B_BIT3 = DFFE( _EQ004, GLOBAL( CLK50M), VCC, VCC, VCC);
_EQ004 = B_BIT3 & !_LC3_A4
# B_BIT2 & _LC3_A4;
-- Node name is 'BDATA0'
-- Equation name is 'BDATA0', type is output
BDATA0 = _LC3_A3;
-- Node name is 'BDATA1'
-- Equation name is 'BDATA1', type is output
BDATA1 = _LC1_A23;
-- Node name is 'BDATA2'
-- Equation name is 'BDATA2', type is output
BDATA2 = _LC8_A23;
-- Node name is 'BDATA3'
-- Equation name is 'BDATA3', type is output
BDATA3 = _LC3_A23;
-- Node name is ':107' = 'BLOCK_COUNTER0'
-- Equation name is 'BLOCK_COUNTER0', location is LC6_B9, type is buried.
BLOCK_COUNTER0 = DFFE( _EQ005, GLOBAL( CLK50M), GLOBAL( VS), VCC, VCC);
_EQ005 = BLOCK_COUNTER0 & !_LC1_B9
# !BLOCK_COUNTER0 & _LC1_B9;
-- Node name is ':106' = 'BLOCK_COUNTER1'
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