adc.tan.rpt

来自「模数转换器AD976采样控制器程序Verilog实现」· RPT 代码 · 共 351 行 · 第 1/4 页

; N/A                                     ; 228.31 MHz ( period = 4.380 ns )                    ; count2[14] ; count2[13] ; clk        ; clk      ; None                        ; None                      ; 4.119 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[11] ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[10] ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[9]  ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[15] ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[14] ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[8]  ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[12] ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 229.94 MHz ( period = 4.349 ns )                    ; count2[5]  ; count2[13] ; clk        ; clk      ; None                        ; None                      ; 4.088 ns                ;
; N/A                                     ; 231.05 MHz ( period = 4.328 ns )                    ; count2[1]  ; nCS~reg0   ; clk        ; clk      ; None                        ; None                      ; 4.067 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[9]  ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[8]  ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[10] ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[11] ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[12] ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[13] ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[14] ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 232.72 MHz ( period = 4.297 ns )                    ; count1[7]  ; count1[15] ; clk        ; clk      ; None                        ; None                      ; 4.036 ns                ;
; N/A                                     ; 233.54 MHz ( period = 4.282 ns )                    ; count1[12] ; count1[2]  ; clk        ; clk      ; None                        ; None                      ; 4.021 ns                ;
; N/A                                     ; 233.54 MHz ( period = 4.282 ns )                    ; count1[12] ; count1[6]  ; clk        ; clk      ; None                        ; None                      ; 4.021 ns                ;
; N/A                                     ; 233.54 MHz ( period = 4.282 ns )                    ; count1[12] ; count1[5]  ; clk        ; clk      ; None                        ; None                      ; 4.021 ns                ;
; N/A                                     ; 233.54 MHz ( period = 4.282 ns )                    ; count1[12] ; count1[4]  ; clk        ; clk      ; None                        ; None                      ; 4.021 ns                ;
; N/A                                     ; 233.54 MHz ( period = 4.282 ns )                    ; count1[12] ; count1[3]  ; clk        ; clk      ; None                        ; None                      ; 4.021 ns                ;
; N/A                                     ; 233.54 MHz ( period = 4.282 ns )                    ; count1[12] ; count1[0]  ; clk        ; clk      ; None                        ; None                      ; 4.021 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;            ;            ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+------------+------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------+
; tco                                                               ;
+-------+--------------+------------+-----------+------+------------+
; Slack ; Required tco ; Actual tco ; From      ; To   ; From Clock ;
+-------+--------------+------------+-----------+------+------------+
; N/A   ; None         ; 7.175 ns   ; R_nC~reg0 ; R_nC ; clk        ;
; N/A   ; None         ; 6.225 ns   ; nCS~reg0  ; nCS  ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Fri Feb 22 16:42:51 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off ADC -c ADC --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 191.98 MHz between source register "count1[8]" and destination register "count1[7]" (period= 5.209 ns)
    Info: + Longest register to register delay is 4.948 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N0; Fanout = 5; REG Node = 'count1[8]'
        Info: 2: + IC(1.220 ns) + CELL(0.114 ns) = 1.334 ns; Loc. = LC_X16_Y12_N0; Fanout = 1; COMB Node = 'LessThan1~206'
        Info: 3: + IC(1.185 ns) + CELL(0.114 ns) = 2.633 ns; Loc. = LC_X16_Y11_N8; Fanout = 17; COMB Node = 'LessThan1~208'
        Info: 4: + IC(1.203 ns) + CELL(1.112 ns) = 4.948 ns; Loc. = LC_X16_Y12_N9; Fanout = 4; REG Node = 'count1[7]'
        Info: Total cell delay = 1.340 ns ( 27.08 % )
        Info: Total interconnect delay = 3.608 ns ( 72.92 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'
            Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y12_N9; Fanout = 4; REG Node = 'count1[7]'
            Info: Total cell delay = 2.180 ns ( 78.36 % )
            Info: Total interconnect delay = 0.602 ns ( 21.64 % )
        Info: - Longest clock path from clock "clk" to source register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'
            Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X16_Y11_N0; Fanout = 5; REG Node = 'count1[8]'
            Info: Total cell delay = 2.180 ns ( 78.36 % )
            Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "clk" to destination pin "R_nC" through register "R_nC~reg0" is 7.175 ns
    Info: + Longest clock path from clock "clk" to source register is 2.782 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 34; CLK Node = 'clk'
        Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X17_Y11_N8; Fanout = 2; REG Node = 'R_nC~reg0'
        Info: Total cell delay = 2.180 ns ( 78.36 % )
        Info: Total interconnect delay = 0.602 ns ( 21.64 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.169 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X17_Y11_N8; Fanout = 2; REG Node = 'R_nC~reg0'
        Info: 2: + IC(2.045 ns) + CELL(2.124 ns) = 4.169 ns; Loc. = PIN_104; Fanout = 0; PIN Node = 'R_nC'
        Info: Total cell delay = 2.124 ns ( 50.95 % )
        Info: Total interconnect delay = 2.045 ns ( 49.05 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Feb 22 16:42:51 2008
    Info: Elapsed time: 00:00:00