pblcd.syr

FPGA 基于PICOBLAZE内核的LCD显示程序,完整,XILINX

    Related source file is "D:/work/vhdl/PBLCD/kcpsm3.vhd".
Unit <kcpsm3> synthesized.


Synthesizing Unit <PBLCD>.
    Related source file is "D:/work/vhdl/PBLCD/PBLCD.vhd".
WARNING:Xst:1778 - Inout <lcd_d> is assigned but never used.
WARNING:Xst:646 - Signal <interrupt_ack> is assigned but never used.
WARNING:Xst:646 - Signal <read_strobe> is assigned but never used.
WARNING:Xst:653 - Signal <interrupt> is used but never assigned. Tied to value 0.
WARNING:Xst:653 - Signal <in_port> is used but never assigned. Tied to value 00000000.
WARNING:Xst:646 - Signal <port_id<7>> is assigned but never used.
WARNING:Xst:646 - Signal <port_id<5:0>> is assigned but never used.
WARNING:Xst:646 - Signal <out_port<3>> is assigned but never used.
WARNING:Xst:653 - Signal <kcpsm3_reset> is used but never assigned. Tied to value 0.
    Found 1-bit register for signal <lcd_rs>.
    Found 1-bit register for signal <lcd_e>.
    Found 4-bit register for signal <lcd_output_data>.
    Found 1-bit register for signal <lcd_rw_control>.
    Summary:
	inferred   7 D-type flip-flop(s).
Unit <PBLCD> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 4
 1-bit register                                        : 3
 4-bit register                                        : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 83
 Flip-Flops                                            : 83

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Loading device for application Rf_Device from file '3s200.nph' in environment D:\Xilinx.

Optimizing unit <PBLCD> ...

Optimizing unit <kcpsm3> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block PBLCD, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : PBLCD.ngr
Top Level Output File Name         : PBLCD
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 8

Cell Usage :
# BELS                             : 203
#      GND                         : 1
#      INV                         : 4
#      LUT1                        : 4
#      LUT2                        : 6
#      LUT3                        : 69
#      LUT4                        : 33
#      MUXCY                       : 39
#      MUXF5                       : 9
#      VCC                         : 1
#      XORCY                       : 37
# FlipFlops/Latches                : 83
#      FD                          : 24
#      FDE                         : 9
#      FDR                         : 30
#      FDRE                        : 8
#      FDRSE                       : 10
#      FDS                         : 2
# RAMS                             : 27
#      RAM16X1D                    : 8
#      RAM32X1S                    : 10
#      RAM64X1S                    : 8
#      RAMB16_S18                  : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 7
#      OBUF                        : 7
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     102  out of   1920     5%  
 Number of Slice Flip Flops:            83  out of   3840     2%  
 Number of 4 input LUTs:               180  out of   3840     4%  
    Number used as logic: 112
    Number used as RAMs: 68
 Number of bonded IOBs:                  8  out of    173     4%  
 Number of BRAMs:                        1  out of     12     8%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+---------------