chengxu.txt

8253定时期的实现。。只介绍方式的代码程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity aaa is
    port(clk,clr,set:in std_logic;
         alm:out std_logic;
         q1,q0:out std_logic_vector(3 downto 0));
end aaa;
architecture aaa_arc of aaa is
begin 
    process(clk)
    variable cnt1,cnt0:std_logic_vector(3 downto 0);
    variable cnt:integer range 0 to 59;
    begin
      if clr='0'then                 -----整体复位
         alm<='0';
         cnt:='0';
         cnt1:="0000";
         cnt0:="0000";
      elsif clk'event and clk='1'then
        if set='0'then                    ------设计数初值
           cnt:='0';
           if cnt0<"1001"then
              cnt0:=cnt0+1;
           else
              cnt0:="0000";
              if cnt1<"1001"then
              cnt1:=cnt1+1;
            else
                cnt1:="0000";
            end if;
            end if;
            else
                if cnt<59 then      ----60分频
                    cnt:=cnt+1;
                else
                    cnt:=0;
                    if cnt0>"0000"then
                        cnt0:=cnt0-1;
                        if cnt1="0000" and cnt0="0000"then  ----判断计时是否结束
                            alm<"1";
                        end if;
                    else
                        cnt0:="1001";
                        if cnt1>"0000"then
                            cnt1:=cnt1-1;
                        else
                            cnt1:="1001";
                        end if;
                    end if;
                end if;
            end if;
        end if;
        q0<=cnt0;
        q1<=cnt1;
        end process;
    end aaa_arc;




library ieee;
use ieee.std_logic_1164.all;
entity ch is
    port(se1:in std_logic;
            a1,a0:in std_logic_vector(3 downto 0);
            q:out std_logic_vector(3 downto 0));
end ch;
architecture ch_arc of ch is
begin
    process(se1,a0,a1)
    begin
        if se1="0"then
            q<=a0;
        else
            q<=a1;
        end if;
    end process;
end ch_arc;






library ieee;
use ieee.std_logic_1164.all;
entity disp is
    port(a:in std_logic_vector(3 downto 0);
        q:out std_logic_vector(6 downto 0));
end disp;
architecture disp_arc of disp is
begin
    process(a)
    begin
        case a is
            when "0000" =>q<="0111111";
            when "0001" =>q<="0000110";
            when "0010" =>q<="1011011";
            when "0011" =>q<="1001111";
            when "0100" =>q<="1100110";
            when "0101" =>q<="1101101";
            when "0110" =>q<="1111101";
            when "0111" =>q<="0000111";
            when "1001" =>q<="1101111";
            when others =>q<="0000000";
        end case;
    end process;
end disp_arc;