ad.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

gen_cm_level : process(ad_data_cm)
begin
	if ad_data_cm >= cml1 and ad_data_cm <= cmh1 then
		t_cm_level <= x"1";
	elsif ad_data_cm >= cml2 and ad_data_cm <= cmh2 then
		t_cm_level <= x"2";	
	elsif ad_data_cm >= cml3 and ad_data_cm <= cmh3 then
		t_cm_level <= x"3";	
	elsif ad_data_cm >= cml4 and ad_data_cm <= cmh4 then
		t_cm_level <= x"4";	
	elsif ad_data_cm >= cml5 and ad_data_cm <= cmh5 then
		t_cm_level <= x"5";	
	elsif ad_data_cm >= cml6 and ad_data_cm <= cmh6 then
		t_cm_level <= x"6";	
	elsif ad_data_cm >= cml7 and ad_data_cm <= cmh7 then
		t_cm_level <= x"7";	
	elsif ad_data_cm >= cml8 and ad_data_cm <= cmh8 then
		t_cm_level <= x"8";	
	elsif ad_data_cm >= cml9 and ad_data_cm <= cmh9 then
		t_cm_level <= x"9";	
	elsif ad_data_cm >= cml10 and ad_data_cm <= cmh10 then
		t_cm_level <= x"a";	
	elsif ad_data_cm >= cml11 and ad_data_cm <= cmh11 then
		t_cm_level <= x"b";	
	elsif ad_data_cm >= cml12 and ad_data_cm <= cmh12 then
		t_cm_level <= x"c";	
	else
		t_cm_level <= x"0";	
	end if;	
end process;

t_p28v_level <= '0' when  ad_data_P28 >= p28v_l else '1';
t_n28v_level <= '0' when  ad_data_n28 <= n28v_h else '1';
t_ref5v_level <= '0' when  ad_data_V5 >= ref5v_l and ad_data_V5 <= ref5v_h else '1';

--建立通道
process(rst,sa,iow,ior)
begin
	if rst='0' then
		t_cda <= "000" ;
	elsif sa=x"c000" and iow='0' then
		t_cda <= sd_in(2 downto 0);
	else 
		if rising_edge(cda_inc) then		
			t_cda <= t_cda + 1;
		end if;
	end if;		
end process;

cda <= t_cda;

cs_com <= '0' when sa=x"c001" else '1';
u_com : wri_reg8 port map(
		iow			=> iow ,--: in std_logic;
		rst			=> rst ,--: in std_logic;
		cs			=> cs_com ,--: in std_logic;
		data_in		=> sd_in ,--: in std_logic_vector(7 downto 0);
		data_out	=> com );--: out std_logic_vector(7 downto 0)


begin_ad : process(rst,sa,iow,end_ad)
begin
	if rst='0' or end_ad='1' then
		beg_ad <= '0';
	else
		if rising_edge(iow) then	
			if sa=x"c001" and sd_in=x"01" then
				beg_ad <= '1';
			end if;	
		end if;
	end if;
end process;

gen_end_ad_tag : process(rst)
begin
	if rst='0' or end_ad='1' then
		t_end_ad_tag <= '0';
	else
		if falling_edge(eoc_state) then			
			t_end_ad_tag <= '1';
		end if;
	end if;		
end process;


process(rst,p1mhz,can_ad,beg_ad)
begin
	if rst='0' then
		st <= st_idle;
		end_ad <= '0';
		ch_cnt <= 0;
		rd_adl <= '1';	
		rd_adh <= '1';
		ad_data_lchk <= x"000";
		ad_data_sd <= x"000";
		ad_data_cm <= x"000";
		ad_data_P28 <= x"000";
		ad_data_N28 <= x"000";
		ad_data_V5	<= x"000";
		ad_charge_time <= 0;
		ad_delay_time <= 0;
		cda_inc <= '1';
		adc_state <= x"00";
	else
		if rising_edge(p1mhz) then	
			case st is
				when st_idle =>
					rd_adl <= '1';	
					rd_adh <= '1';	
					ad_charge_time <= 0;
					ad_delay_time <= 0;
					cda_inc <= '1';
					if beg_ad='1' then
						st <= st_charge;
						end_ad <= '0';
					else
						st <= st_idle;
					end if;
				when st_charge =>
					if ad_charge_time < 20 then
						ad_charge_time	<= ad_charge_time + 1;
						st <= st_charge;
					else
						st <= st_start_ad;	
						ad_charge_time <= 0;
					end if;	
				when st_start_ad =>
					st <= st_ad_wait;
					start_ad <= '1';
					ad_delay_time <= 0;
				when st_ad_wait =>
					if ad_delay_time < 10 then
						ad_delay_time <= ad_delay_time + 1; 
						start_ad <= '1';
						st <= st_ad_wait;
					else
						ad_delay_time <= 0;
						start_ad <= '0';
						st <= st_ad_wait0;
					end if;	
				when st_ad_wait0 =>
					if t_end_ad_tag='0' and ad_delay_time < 100 then
						ad_delay_time <= ad_delay_time + 1;
						st <= st_ad_wait0;
					elsif t_end_ad_tag='1' and com=x"01" then --单通道转换
						ad_delay_time <= 0;
						st <= st_ad_end;
					elsif t_end_ad_tag='1' and com=x"03" then --连续转换	
						st <= st_read_adl;	
						
						----------------
					else
						st <= st_ad_error;
						ad_delay_time <= 0;
					end if;		
				when st_read_adl =>
					if t_adc_state="10" then --AD转换正常。
						rd_adl <= '0';	
						st <= st_read_adl_wait;
					else
						st <= st_ad_error;
					end if;	
				when st_read_adl_wait =>
					case t_cda is
						when "000" => ad_data_lchk(7 downto 0) <= sd;
						when "001" => ad_data_sd(7 downto 0) <= sd;
						when "010" => ad_data_cm(7 downto 0) <= sd;
						when "011" => ad_data_P28(7 downto 0) <= sd;
						when "100" => ad_data_N28(7 downto 0) <= sd;
						when "101" => ad_data_V5(7 downto 0) <= sd;
						when others => ad_data_temp(7 downto 0) <=sd;
					end case;	
					st <= st_read_adl_wait0;
				when st_read_adl_wait0 =>
					rd_adl <= '1';	
					st <= st_read_adh;
				when st_read_adh =>
					rd_adh <= '0';
					st <= st_read_adh_wait;
				when st_read_adh_wait =>
					case t_cda is
						when "000" => ad_data_lchk(11 downto 8) <= sd(3 downto 0);
						when "001" => ad_data_sd(11 downto 8) <= sd(3 downto 0);
						when "010" => ad_data_cm(11 downto 8) <= sd(3 downto 0);
						when "011" => ad_data_P28(11 downto 8) <= sd(3 downto 0);
						when "100" => ad_data_N28(11 downto 8) <= sd(3 downto 0);
						when "101" => ad_data_V5(11 downto 8) <= sd(3 downto 0);
						when others => ad_data_temp(11 downto 8) <= sd(3 downto 0);
					end case;	
					st <= st_read_adh_wait0;
				when st_read_adh_wait0 =>
					rd_adh <= '1';
				when st_ad_next	=>
					if com=x"01" then
						end_ad <= '1';
						st <= st_ad_end ;
					else
						st <= st_con_ad;
					end if;		
				when st_con_ad =>
--					if tran_all_ad='1' and t_cda < 5 then	
--						st <= st_cda_inc;
--					else
--						st <= st_ad_end;
--						end_ad <= '1';
--					end if;								
				when st_cda_inc =>						
					cda_inc <= '0'; 
					st <= st_cda_inc_wait;
				when st_cda_inc_wait =>	
					cda_inc <= '1';
					st <= st_charge;
				when st_ad_end =>
					end_ad <= '1';
					adc_state <= x"80"; --正常结束
					st <= st_ad_end_wait;
				when st_ad_end_wait =>
					end_ad <= '0';
					st <= st_idle;	
					
				when st_ad_error =>
--					adc_state <= "11";
--					st <= st_idle;
--				when st_error_wait =>
--					if tran_all_ad = '0' then
--						st <= st_error_wait;
--					else
--						st <= st_idle;	
						end_ad <= '1';
--					end if;	
				when others =>	
					st <= st_idle;
			end case;
		end if;
	end if;								

end process;

end architecture;