sig_adc.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

--功能：执行单一通道的ad转换
--输入：启动信号can_ad
--
--输出：
--返回状态：
--			adc_st=x"80"  正常结束。
--          adc_st="00"   复位 
--          adc_st=x"03"  AD未正常结束，超时。

LIBRARY IEEE;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity sig_adc is port(
		rst				: in std_logic;
		sa				: in std_logic_vector(15 downto 0);
		ad_in			: in std_logic_vector(7 downto 0);
		can_adc			: in std_logic;
		iow				: in std_logic;
		p12mhz			: in std_logic;
		eoc_state		: in std_logic;
		sd				: in std_logic_vector(7 downto 0);
		rd_adl			: out std_logic;
		rd_adh			: out std_logic;
		start_ad 		: out std_logic;
	--ad 转换状态。00=转换结束；11=转换超时。	
		adc_state		: out std_logic_vector(7 downto 0);
		ad_data			: out std_logic_vector(11 downto 0)


);
end entity ;

architecture ad of sig_adc is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;
		
	
signal st : integer range 0 to 31;
		
constant st_idle 					: integer	:= 0;
constant st_start_ad 				: integer	:= 1;	
constant st_ad_wait					: integer	:= 2;
constant st_ad_wait0				: integer	:= 3;
constant st_read_adl				: integer	:= 4;
constant st_read_adl_wait			: integer	:= 5;
constant st_read_adl_wait0			: integer	:= 6;
constant st_read_adh				: integer	:= 7;
constant st_read_adh_wait			: integer	:= 8;
constant st_read_adh_wait0			: integer	:= 9;
constant st_ad_next					: integer	:= 10;
constant st_ad_end					: integer	:= 11;
constant st_con_ad					: integer	:= 12;
constant st_ad_error				: integer	:= 13;
constant st_charge					: integer	:= 14;
constant st_cda_inc					: integer	:= 15;
constant st_cda_inc_wait			: integer	:= 16;
constant st_ad_end_wait				: integer	:= 17;
constant st_read_adl_end			: integer	:= 18;
constant st_read_adh_end			: integer	:= 19;
constant st_read_adl_end_wait		: integer	:= 20;
constant st_read_adh_end_wait		: integer	:= 21;
constant st_st_ad_end_wait			: integer	:= 22;
constant st_st_ad_end_wait0			: integer	:= 23;
constant st_ad_error_wait			: integer	:= 24;
constant st_ad_error_wait0			: integer	:= 25;
constant st_read_adh_endx			: integer	:= 26;
constant st_read_adl_endx			: integer	:= 27;


signal t_sig_adc,t_sig_adc_end : std_logic;
signal ad_charge_time : integer range 0 to 1500;
signal ad_delay_time : integer range 0 to 1000;
signal can_ad : std_logic;
signal t_setup_adc_state : std_logic;
signal t_t_sig_adc_end_tag : std_logic;
---------sig_ad data---------------------------
constant read_data_time 		: integer := 800; 
constant distance_time 			: integer := 900; 
constant delay_time 			: integer := 300; 
constant charge_time 			: integer := 1400;
constant start_ad_time 			: integer := 200;
constant change_wait_time 		: integer := 800;
constant read_data_up_wait		: integer := 400;

 
begin


setup_sig_adc : process(rst,t_sig_adc_end,can_adc)
begin
	if rst='0' or t_sig_adc_end = '1' then
		t_sig_adc <= '0';
	else
		if rising_edge(can_adc)	then
			 t_sig_adc <= '1';
		end if;
	end if;		
end process;


gen_t_sig_adc_end_tag : process(rst,t_sig_adc_end,eoc_state)
begin
	if rst='0' or t_sig_adc_end='1' then
		t_t_sig_adc_end_tag <= '0';
	else
		if rising_edge(eoc_state) then			
			t_t_sig_adc_end_tag <= '1';
		end if;
	end if;		
end process;


process(rst,p12mhz,can_ad,t_sig_adc)
begin
	if rst='0' then
		st <= st_idle;
		t_sig_adc_end <= '0';
		rd_adl <= '1';	
		rd_adh <= '1';
		ad_charge_time <= 0;
		ad_delay_time <= 0;
		adc_state <= x"00";
		t_setup_adc_state <= '1';
	else
		if rising_edge(p12mhz) then	
			case st is
				when st_idle =>
					rd_adl <= '1';	
					rd_adh <= '1';	
					ad_charge_time <= 0;
					ad_delay_time <= 0;
					t_sig_adc_end <= '0';
					t_setup_adc_state <= '1'; 
					if t_sig_adc='1' then
						adc_state <= x"00";
						st <= st_charge;
					else
						st <= st_idle;
					end if;
				when st_charge =>
					if ad_charge_time < charge_time then
						ad_charge_time	<= ad_charge_time + 1;
						st <= st_charge;
					else
						st <= st_start_ad;	
						ad_charge_time <= 0;
					end if;	
				when st_start_ad =>
					st <= st_ad_wait;
					start_ad <= '1';
					ad_delay_time <= 0;
				when st_ad_wait =>
					if ad_delay_time < start_ad_time then
						ad_delay_time <= ad_delay_time + 1; 
						start_ad <= '1';
						st <= st_ad_wait;
					else
						ad_delay_time <= 0;
						start_ad <= '0';
						st <= st_ad_wait0;
					end if;	
				when st_ad_wait0 =>
					if t_t_sig_adc_end_tag='0' and ad_delay_time < change_wait_time then
						ad_delay_time <= ad_delay_time + 1;
						st <= st_ad_wait0;
					elsif t_t_sig_adc_end_tag='1' then 
						ad_delay_time <= 0;
						st <= st_read_adl;
					else
						st <= st_ad_error;
						ad_delay_time <= 0;
					end if;		
				when st_read_adl =>
					rd_adl <= '0';	
					st <= st_read_adl_wait;
				when st_read_adl_wait =>
					if ad_delay_time < read_data_time then
						st <= st_read_adl_wait;
						ad_delay_time <= ad_delay_time + 1;
					else
						ad_delay_time <= 0; 
						st <= st_read_adl_wait0;
					end if;	
				when st_read_adl_wait0 =>
					ad_data(7 downto 0) <= sd(7 downto 0);
					ad_delay_time <= 0;
					st <= st_read_adl_endx;
				when st_read_adl_endx =>
					if ad_delay_time < read_data_up_wait then
						ad_delay_time <= ad_delay_time + 1;
						st <= st_read_adl_endx;
					else
						ad_delay_time <= 0;
						st <= st_read_adl_end;
					end if;	
				when st_read_adl_end =>
					rd_adl <= '1';
					ad_delay_time <= 0;	
					st <= st_read_adl_end_wait;
				when st_read_adl_end_wait =>
					if ad_delay_time < distance_time then	
						ad_delay_time <= ad_delay_time + 1;
						st <= st_read_adl_end_wait;
					else
						st <= st_read_adh;
						ad_delay_time <= 0;	
					end if;	
				when st_read_adh =>
					st <= st_read_adh_wait;
					rd_adh <= '0';
				when st_read_adh_wait =>
					if ad_delay_time < read_data_time then
						ad_delay_time <= ad_delay_time + 1;
						st <= st_read_adh_wait;
					else
						ad_delay_time <= 0;
						st <= st_read_adh_wait0;
					end if;	
				when st_read_adh_wait0 =>
					ad_data(11 downto 8) <= sd(3 downto 0);
					ad_delay_time <= 0;
					st <= st_read_adh_endx;
				when st_read_adh_endx =>
					if ad_delay_time < read_data_up_wait then
						ad_delay_time <= ad_delay_time + 1;
						st <= st_read_adh_endx;
					else
						ad_delay_time <= 0;	
						st <= st_read_adh_end ;
					end if;		
				when st_read_adh_end =>
					rd_adh <= '1';
					ad_delay_time <= 0;
					st <= st_read_adh_end_wait;
				when st_read_adh_end_wait =>
					if ad_delay_time < 300 then
						ad_delay_time <= ad_delay_time + 1;
						st <= st_read_adh_end_wait;
					else
						st <= st_ad_end;
					end if;	
				when st_ad_end =>--
					t_setup_adc_state <= '0';
					adc_state <= x"80";
					st <= st_st_ad_end_wait;
				when st_st_ad_end_wait =>
					st <= st_st_ad_end_wait0;
				when st_st_ad_end_wait0 =>
					t_setup_adc_state <= '1';		
					st <= st_idle;
					t_sig_adc_end <= '1';	
				when st_ad_error =>
					adc_state <= x"03"; --转换超时
					t_setup_adc_state <= '0';
					st <= st_ad_error_wait;
				when st_ad_error_wait =>
					st <= st_ad_error_wait0;
				when st_ad_error_wait0 =>
					t_setup_adc_state <= '1';		
					t_sig_adc_end <= '1';
					st <= st_idle;
				when others =>	
					st <= st_idle;
			end case;
		end if;
	end if;								

end process;

end architecture;