cpu.tan.qmsg

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

{ "Info" "ITDB_TH_RESULT" "rx8:u_rx8\|t_data\[6\] rxd p12mhz 5.500 ns register " "Info: th for register \"rx8:u_rx8\|t_data\[6\]\" (data pin = \"rxd\", clock pin = \"p12mhz\") is 5.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "p12mhz destination 6.900 ns + Longest register " "Info: + Longest clock path from clock \"p12mhz\" to destination register is 6.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns p12mhz 1 CLK PIN_125 141 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_125; Fanout = 141; CLK Node = 'p12mhz'" {  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "" { p12mhz } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns gen_1mhz:u_p1mhz\|P1MHz 2 REG LC1_D10 67 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC1_D10; Fanout = 67; REG Node = 'gen_1mhz:u_p1mhz\|P1MHz'" {  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "0.700 ns" { p12mhz gen_1mhz:u_p1mhz|P1MHz } "NODE_NAME" } "" } } { "gen_1mhz.vhd" "" { Text "D:/weng/yu7b/ycpu22X/gen_1mhz.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(0.400 ns) 5.900 ns rx8:u_rx8\|data_clk:u_data_clk\|data_clk 3 REG LC2_C11 19 " "Info: 3: + IC(3.300 ns) + CELL(0.400 ns) = 5.900 ns; Loc. = LC2_C11; Fanout = 19; REG Node = 'rx8:u_rx8\|data_clk:u_data_clk\|data_clk'" {  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "3.700 ns" { gen_1mhz:u_p1mhz|P1MHz rx8:u_rx8|data_clk:u_data_clk|data_clk } "NODE_NAME" } "" } } { "data_clk.vhd" "" { Text "D:/weng/yu7b/ycpu22X/data_clk.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.000 ns) 6.900 ns rx8:u_rx8\|t_data\[6\] 4 REG LC3_C4 1 " "Info: 4: + IC(1.000 ns) + CELL(0.000 ns) = 6.900 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 'rx8:u_rx8\|t_data\[6\]'" {  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "1.000 ns" { rx8:u_rx8|data_clk:u_data_clk|data_clk rx8:u_rx8|t_data[6] } "NODE_NAME" } "" } } { "rx8.vhd" "" { Text "D:/weng/yu7b/ycpu22X/rx8.vhd" 82 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.300 ns 33.33 % " "Info: Total cell delay = 2.300 ns ( 33.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns 66.67 % " "Info: Total interconnect delay = 4.600 ns ( 66.67 % )" {  } {  } 0}  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "6.900 ns" { p12mhz gen_1mhz:u_p1mhz|P1MHz rx8:u_rx8|data_clk:u_data_clk|data_clk rx8:u_rx8|t_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "6.900 ns" { p12mhz p12mhz~out gen_1mhz:u_p1mhz|P1MHz rx8:u_rx8|data_clk:u_data_clk|data_clk rx8:u_rx8|t_data[6] } { 0.000ns 0.000ns 0.300ns 3.300ns 1.000ns } { 0.000ns 1.500ns 0.400ns 0.400ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.000 ns + " "Info: + Micro hold delay of destination is 1.000 ns" {  } { { "rx8.vhd" "" { Text "D:/weng/yu7b/ycpu22X/rx8.vhd" 82 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns rxd 1 CLK PIN_55 8 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_55; Fanout = 8; CLK Node = 'rxd'" {  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "" { rxd } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.700 ns) 2.400 ns rx8:u_rx8\|t_data\[6\] 2 REG LC3_C4 1 " "Info: 2: + IC(0.200 ns) + CELL(0.700 ns) = 2.400 ns; Loc. = LC3_C4; Fanout = 1; REG Node = 'rx8:u_rx8\|t_data\[6\]'" {  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "0.900 ns" { rxd rx8:u_rx8|t_data[6] } "NODE_NAME" } "" } } { "rx8.vhd" "" { Text "D:/weng/yu7b/ycpu22X/rx8.vhd" 82 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 91.67 % " "Info: Total cell delay = 2.200 ns ( 91.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.200 ns 8.33 % " "Info: Total interconnect delay = 0.200 ns ( 8.33 % )" {  } {  } 0}  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "2.400 ns" { rxd rx8:u_rx8|t_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.400 ns" { rxd rxd~out rx8:u_rx8|t_data[6] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.500ns 0.700ns } } }  } 0}  } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "6.900 ns" { p12mhz gen_1mhz:u_p1mhz|P1MHz rx8:u_rx8|data_clk:u_data_clk|data_clk rx8:u_rx8|t_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "6.900 ns" { p12mhz p12mhz~out gen_1mhz:u_p1mhz|P1MHz rx8:u_rx8|data_clk:u_data_clk|data_clk rx8:u_rx8|t_data[6] } { 0.000ns 0.000ns 0.300ns 3.300ns 1.000ns } { 0.000ns 1.500ns 0.400ns 0.400ns 0.000ns } } } { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "2.400 ns" { rxd rx8:u_rx8|t_data[6] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "2.400 ns" { rxd rxd~out rx8:u_rx8|t_data[6] } { 0.000ns 0.000ns 0.200ns } { 0.000ns 1.500ns 0.700ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 14 13:47:56 2007 " "Info: Processing ended: Fri Dec 14 13:47:56 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}