📄 cpu.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "14 " "Warning: Found 14 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "timer:U_TIMER\|t_1s " "Info: Detected ripple clock \"timer:U_TIMER\|t_1s\" as buffer" { } { { "timer.vhd" "" { Text "D:/weng/yu7b/ycpu22X/timer.vhd" 44 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "timer:U_TIMER\|t_1s" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "timer:U_TIMER\|t_60s " "Info: Detected ripple clock \"timer:U_TIMER\|t_60s\" as buffer" { } { { "timer.vhd" "" { Text "D:/weng/yu7b/ycpu22X/timer.vhd" 60 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "timer:U_TIMER\|t_60s" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "timer:U_TIMER\|t_60min " "Info: Detected ripple clock \"timer:U_TIMER\|t_60min\" as buffer" { } { { "timer.vhd" "" { Text "D:/weng/yu7b/ycpu22X/timer.vhd" 78 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "timer:U_TIMER\|t_60min" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "rx8:u_rx8\|data_clk:u_data_clk\|data_clk " "Info: Detected ripple clock \"rx8:u_rx8\|data_clk:u_data_clk\|data_clk\" as buffer" { } { { "data_clk.vhd" "" { Text "D:/weng/yu7b/ycpu22X/data_clk.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "rx8:u_rx8\|data_clk:u_data_clk\|data_clk" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "rx8:u_rx8\|en_rx " "Info: Detected ripple clock \"rx8:u_rx8\|en_rx\" as buffer" { } { { "rx8.vhd" "" { Text "D:/weng/yu7b/ycpu22X/rx8.vhd" 53 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "rx8:u_rx8\|en_rx" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "do_adc:u_ad\|t_sig_adc " "Info: Detected ripple clock \"do_adc:u_ad\|t_sig_adc\" as buffer" { } { { "do_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/do_adc.vhd" 394 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "do_adc:u_ad\|t_sig_adc" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "read_return_pre_set:u_rx_tx\|rx16:u_rx\|rx_tag " "Info: Detected ripple clock \"read_return_pre_set:u_rx_tx\|rx16:u_rx\|rx_tag\" as buffer" { } { { "rx16.vhd" "" { Text "D:/weng/yu7b/ycpu22X/rx16.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "read_return_pre_set:u_rx_tx\|rx16:u_rx\|rx_tag" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "read_return_pre_set:u_rx_tx\|rx16:u_rx\|en_rx " "Info: Detected ripple clock \"read_return_pre_set:u_rx_tx\|rx16:u_rx\|en_rx\" as buffer" { } { { "rx16.vhd" "" { Text "D:/weng/yu7b/ycpu22X/rx16.vhd" 52 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "read_return_pre_set:u_rx_tx\|rx16:u_rx\|en_rx" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "tx8:u_tx8\|data_clk:u_data_clk\|data_clk " "Info: Detected ripple clock \"tx8:u_tx8\|data_clk:u_data_clk\|data_clk\" as buffer" { } { { "data_clk.vhd" "" { Text "D:/weng/yu7b/ycpu22X/data_clk.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "tx8:u_tx8\|data_clk:u_data_clk\|data_clk" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "gen_1mhz:u_p1mhz\|p1khz " "Info: Detected ripple clock \"gen_1mhz:u_p1mhz\|p1khz\" as buffer" { } { { "gen_1mhz.vhd" "" { Text "D:/weng/yu7b/ycpu22X/gen_1mhz.vhd" 13 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gen_1mhz:u_p1mhz\|p1khz" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "read_return_pre_set:u_rx_tx\|t_start_tx " "Info: Detected ripple clock \"read_return_pre_set:u_rx_tx\|t_start_tx\" as buffer" { } { { "read_return_pre_set.vhd" "" { Text "D:/weng/yu7b/ycpu22X/read_return_pre_set.vhd" 106 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "read_return_pre_set:u_rx_tx\|t_start_tx" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "read_return_pre_set:u_rx_tx\|rx16:u_rx\|data_clk:u_data_clk\|data_clk " "Info: Detected ripple clock \"read_return_pre_set:u_rx_tx\|rx16:u_rx\|data_clk:u_data_clk\|data_clk\" as buffer" { } { { "data_clk.vhd" "" { Text "D:/weng/yu7b/ycpu22X/data_clk.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "read_return_pre_set:u_rx_tx\|rx16:u_rx\|data_clk:u_data_clk\|data_clk" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "gen_1mhz:u_p1mhz\|P1MHz " "Info: Detected ripple clock \"gen_1mhz:u_p1mhz\|P1MHz\" as buffer" { } { { "gen_1mhz.vhd" "" { Text "D:/weng/yu7b/ycpu22X/gen_1mhz.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gen_1mhz:u_p1mhz\|P1MHz" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "read_return_pre_set:u_rx_tx\|tx16:u_tx\|data_clk:u_data_clk\|data_clk " "Info: Detected ripple clock \"read_return_pre_set:u_rx_tx\|tx16:u_tx\|data_clk:u_data_clk\|data_clk\" as buffer" { } { { "data_clk.vhd" "" { Text "D:/weng/yu7b/ycpu22X/data_clk.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "read_return_pre_set:u_rx_tx\|tx16:u_tx\|data_clk:u_data_clk\|data_clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "p12mhz register do_adc:u_ad\|sig_adc:u_sig_adc\|t_sig_adc register do_adc:u_ad\|sig_adc:u_sig_adc\|st\[1\] 65.79 MHz 15.2 ns Internal " "Info: Clock \"p12mhz\" has Internal fmax of 65.79 MHz between source register \"do_adc:u_ad\|sig_adc:u_sig_adc\|t_sig_adc\" and destination register \"do_adc:u_ad\|sig_adc:u_sig_adc\|st\[1\]\" (period= 15.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.400 ns + Longest register register " "Info: + Longest register to register delay is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns do_adc:u_ad\|sig_adc:u_sig_adc\|t_sig_adc 1 REG LC3_E20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_E20; Fanout = 4; REG Node = 'do_adc:u_ad\|sig_adc:u_sig_adc\|t_sig_adc'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "" { do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } "NODE_NAME" } "" } } { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 104 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.100 ns) 1.300 ns do_adc:u_ad\|sig_adc:u_sig_adc\|Mux~686 2 COMB LC6_E20 1 " "Info: 2: + IC(0.200 ns) + CELL(1.100 ns) = 1.300 ns; Loc. = LC6_E20; Fanout = 1; COMB Node = 'do_adc:u_ad\|sig_adc:u_sig_adc\|Mux~686'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "1.300 ns" { do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|Mux~686 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(0.900 ns) 3.200 ns do_adc:u_ad\|sig_adc:u_sig_adc\|Mux~1098 3 COMB LC6_E19 1 " "Info: 3: + IC(1.000 ns) + CELL(0.900 ns) = 3.200 ns; Loc. = LC6_E19; Fanout = 1; COMB Node = 'do_adc:u_ad\|sig_adc:u_sig_adc\|Mux~1098'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "1.900 ns" { do_adc:u_ad|sig_adc:u_sig_adc|Mux~686 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1098 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.100 ns) 4.500 ns do_adc:u_ad\|sig_adc:u_sig_adc\|Mux~1099 4 COMB LC8_E19 1 " "Info: 4: + IC(0.200 ns) + CELL(1.100 ns) = 4.500 ns; Loc. = LC8_E19; Fanout = 1; COMB Node = 'do_adc:u_ad\|sig_adc:u_sig_adc\|Mux~1099'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "1.300 ns" { do_adc:u_ad|sig_adc:u_sig_adc|Mux~1098 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1099 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.700 ns) 5.400 ns do_adc:u_ad\|sig_adc:u_sig_adc\|st\[1\] 5 REG LC1_E19 84 " "Info: 5: + IC(0.200 ns) + CELL(0.700 ns) = 5.400 ns; Loc. = LC1_E19; Fanout = 84; REG Node = 'do_adc:u_ad\|sig_adc:u_sig_adc\|st\[1\]'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "0.900 ns" { do_adc:u_ad|sig_adc:u_sig_adc|Mux~1099 do_adc:u_ad|sig_adc:u_sig_adc|st[1] } "NODE_NAME" } "" } } { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 135 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 70.37 % " "Info: Total cell delay = 3.800 ns ( 70.37 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 29.63 % " "Info: Total interconnect delay = 1.600 ns ( 29.63 % )" { } { } 0} } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "5.400 ns" { do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|Mux~686 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1098 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1099 do_adc:u_ad|sig_adc:u_sig_adc|st[1] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.400 ns" { do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|Mux~686 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1098 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1099 do_adc:u_ad|sig_adc:u_sig_adc|st[1] } { 0.000ns 0.200ns 1.000ns 0.200ns 0.200ns } { 0.000ns 1.100ns 0.900ns 1.100ns 0.700ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.200 ns - Smallest " "Info: - Smallest clock skew is -1.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "p12mhz destination 1.800 ns + Shortest register " "Info: + Shortest clock path from clock \"p12mhz\" to destination register is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns p12mhz 1 CLK PIN_125 141 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_125; Fanout = 141; CLK Node = 'p12mhz'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "" { p12mhz } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.000 ns) 1.800 ns do_adc:u_ad\|sig_adc:u_sig_adc\|st\[1\] 2 REG LC1_E19 84 " "Info: 2: + IC(0.300 ns) + CELL(0.000 ns) = 1.800 ns; Loc. = LC1_E19; Fanout = 84; REG Node = 'do_adc:u_ad\|sig_adc:u_sig_adc\|st\[1\]'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "0.300 ns" { p12mhz do_adc:u_ad|sig_adc:u_sig_adc|st[1] } "NODE_NAME" } "" } } { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 135 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 83.33 % " "Info: Total cell delay = 1.500 ns ( 83.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.300 ns 16.67 % " "Info: Total interconnect delay = 0.300 ns ( 16.67 % )" { } { } 0} } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "1.800 ns" { p12mhz do_adc:u_ad|sig_adc:u_sig_adc|st[1] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { p12mhz p12mhz~out do_adc:u_ad|sig_adc:u_sig_adc|st[1] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "p12mhz source 3.000 ns - Longest register " "Info: - Longest clock path from clock \"p12mhz\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns p12mhz 1 CLK PIN_125 141 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_125; Fanout = 141; CLK Node = 'p12mhz'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "" { p12mhz } "NODE_NAME" } "" } } { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.400 ns) 2.200 ns do_adc:u_ad\|t_sig_adc 2 REG LC2_E21 1 " "Info: 2: + IC(0.300 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC2_E21; Fanout = 1; REG Node = 'do_adc:u_ad\|t_sig_adc'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "0.700 ns" { p12mhz do_adc:u_ad|t_sig_adc } "NODE_NAME" } "" } } { "do_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/do_adc.vhd" 394 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.000 ns) 3.000 ns do_adc:u_ad\|sig_adc:u_sig_adc\|t_sig_adc 3 REG LC3_E20 4 " "Info: 3: + IC(0.800 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3_E20; Fanout = 4; REG Node = 'do_adc:u_ad\|sig_adc:u_sig_adc\|t_sig_adc'" { } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "0.800 ns" { do_adc:u_ad|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } "NODE_NAME" } "" } } { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 104 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 63.33 % " "Info: Total cell delay = 1.900 ns ( 63.33 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 36.67 % " "Info: Total interconnect delay = 1.100 ns ( 36.67 % )" { } { } 0} } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "3.000 ns" { p12mhz do_adc:u_ad|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { p12mhz p12mhz~out do_adc:u_ad|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } { 0.000ns 0.000ns 0.300ns 0.800ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } } 0} } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "1.800 ns" { p12mhz do_adc:u_ad|sig_adc:u_sig_adc|st[1] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { p12mhz p12mhz~out do_adc:u_ad|sig_adc:u_sig_adc|st[1] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "3.000 ns" { p12mhz do_adc:u_ad|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { p12mhz p12mhz~out do_adc:u_ad|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } { 0.000ns 0.000ns 0.300ns 0.800ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" { } { { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 104 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.600 ns + " "Info: + Micro setup delay of destination is 0.600 ns" { } { { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 135 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 104 -1 0 } } { "sig_adc.vhd" "" { Text "D:/weng/yu7b/ycpu22X/sig_adc.vhd" 135 -1 0 } } } 0} } { { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "5.400 ns" { do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|Mux~686 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1098 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1099 do_adc:u_ad|sig_adc:u_sig_adc|st[1] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "5.400 ns" { do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|Mux~686 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1098 do_adc:u_ad|sig_adc:u_sig_adc|Mux~1099 do_adc:u_ad|sig_adc:u_sig_adc|st[1] } { 0.000ns 0.200ns 1.000ns 0.200ns 0.200ns } { 0.000ns 1.100ns 0.900ns 1.100ns 0.700ns } } } { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "1.800 ns" { p12mhz do_adc:u_ad|sig_adc:u_sig_adc|st[1] } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "1.800 ns" { p12mhz p12mhz~out do_adc:u_ad|sig_adc:u_sig_adc|st[1] } { 0.000ns 0.000ns 0.300ns } { 0.000ns 1.500ns 0.000ns } } } { "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" "" { Report "D:/weng/yu7b/ycpu22X/db/cpu_cmp.qrpt" Compiler "cpu" "UNKNOWN" "V1" "D:/weng/yu7b/ycpu22X/db/cpu.quartus_db" { Floorplan "D:/weng/yu7b/ycpu22X/" "" "3.000 ns" { p12mhz do_adc:u_ad|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } "NODE_NAME" } "" } } { "c:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus42/bin/Technology_Viewer.qrui" "3.000 ns" { p12mhz p12mhz~out do_adc:u_ad|t_sig_adc do_adc:u_ad|sig_adc:u_sig_adc|t_sig_adc } { 0.000ns 0.000ns 0.300ns 0.800ns } { 0.000ns 1.500ns 0.400ns 0.000ns } } } } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "iow " "Info: No valid register-to-register data paths exist for clock \"iow\"" { } { } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ale " "Info: No valid register-to-register data paths exist for clock \"ale\"" { } { } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "urgency_put_opt_in " "Info: No valid register-to-register data paths exist for clock \"urgency_put_opt_in\"" { } { } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ready_reset_opt_in " "Info: No valid register-to-register data paths exist for clock \"ready_reset_opt_in\"" { } { } 0}
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