cpu.tan.qmsg

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 14 13:47:54 2007 " "Info: Processing started: Fri Dec 14 13:47:54 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off cpu -c cpu " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off cpu -c cpu" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "p12mhz " "Info: Assuming node \"p12mhz\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 8 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "p12mhz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "iow " "Info: Assuming node \"iow\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 27 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "iow" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ale " "Info: Assuming node \"ale\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 33 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "ale" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "urgency_put_opt_in " "Info: Assuming node \"urgency_put_opt_in\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 36 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "urgency_put_opt_in" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ready_reset_opt_in " "Info: Assuming node \"ready_reset_opt_in\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 37 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "ready_reset_opt_in" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "set_rx " "Info: Assuming node \"set_rx\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 12 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "set_rx" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "eoc_state " "Info: Assuming node \"eoc_state\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 32 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "eoc_state" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rxd " "Info: Assuming node \"rxd\" is an undefined clock" {  } { { "cpu.vhd" "" { Text "D:/weng/yu7b/ycpu22X/cpu.vhd" 60 -1 0 } } { "c:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "rxd" } } } }  } 0}  } {  } 0}