📄 writeled_and_tx.vwf

📁 这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试
💻 VWF
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	SIMULATION_TIME = 3000000.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("set_tx")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("ad")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("ad[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("ad[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("ad[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("ad[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("ad[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("ad[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("ad[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("ad[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "ad";
}

SIGNAL("iow")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("p1mhz")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("rst")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("sa")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 16;
	LSB_INDEX = 0;
	DIRECTION = INPUT;
	PARENT = "";
}

SIGNAL("sa[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("sa[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "sa";
}

SIGNAL("x_on_tx")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("o_st")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 4;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("o_st[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "o_st";
}

SIGNAL("o_st[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "o_st";
}

SIGNAL("o_st[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "o_st";
}

SIGNAL("o_st[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "o_st";
}

SIGNAL("o_start_tx")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "";
}

TRANSITION_LIST("set_tx")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 78515.9;
		LEVEL 0 FOR 168002.1;
		LEVEL 1 FOR 1.1;
		LEVEL 0 FOR 223996.5;
		LEVEL 1 FOR 0.2;
		LEVEL 0 FOR 1.2;
		LEVEL 1 FOR 1.9;
		LEVEL 0 FOR 111996.9;
		LEVEL 1 FOR 141000.1;
		LEVEL 0 FOR 56003.0;
		LEVEL 1 FOR 55998.1;
		LEVEL 0 FOR 56001.0;
		LEVEL 1 FOR 1.1;
		LEVEL 0 FOR 0.2;
		LEVEL 1 FOR 56000.0;
		LEVEL 0 FOR 167996.3;
		LEVEL 1 FOR 0.2;
		LEVEL 0 FOR 1.2;
		LEVEL 1 FOR 56000.0;
		LEVEL 0 FOR 55998.8;
		LEVEL 1 FOR 1772484.2;
	}
}

TRANSITION_LIST("ad[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("ad[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 23680.0;
		LEVEL 1 FOR 38030.0;
		LEVEL 0 FOR 2938290.0;
	}
}

TRANSITION_LIST("ad[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("ad[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("ad[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("ad[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 23680.0;
		LEVEL 1 FOR 38030.0;
		LEVEL 0 FOR 2938290.0;
	}
}

TRANSITION_LIST("ad[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("ad[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 23680.0;
		LEVEL 1 FOR 38030.0;
		LEVEL 0 FOR 2938290.0;
	}
}

TRANSITION_LIST("iow")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 32235.0;
		LEVEL 0 FOR 17995.0;
		LEVEL 1 FOR 2949770.0;
	}
}

TRANSITION_LIST("p1mhz")
{
	NODE
	{
		REPEAT = 1;
		NODE
		{
			REPEAT = 3000;
			LEVEL 0 FOR 500.0;
			LEVEL 1 FOR 500.0;
		}
	}
}

TRANSITION_LIST("rst")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 465.0;
		LEVEL 0 FOR 3740.0;
		LEVEL 1 FOR 2995795.0;
	}
}

TRANSITION_LIST("sa[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12915.0;
		LEVEL 1 FOR 55970.0;
		LEVEL 0 FOR 2931115.0;
	}
}

TRANSITION_LIST("sa[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 12915.0;
		LEVEL 1 FOR 55970.0;
		LEVEL 0 FOR 2931115.0;
	}
}

TRANSITION_LIST("sa[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 3000000.0;
	}
}

TRANSITION_LIST("sa[12]")
12 下一页
💿 文件大小 1550 K
👤 上传用户 feitiandy001
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#ALTERA #VHDL #FLEX #422
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