tx8.vhd

这是一个用VHDL开发的RS422通讯程序,在ALTERA FLEX EPF10K上通过了测试

--一次发送8位数据。当start_tx为1时，开始发送8位数据。
--第1位是低电平起始位，以后8位数据位，最后变高电平。

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity tx8 is port(
		rst			: in std_logic;
		p1mhz		: in std_logic;
		sa			: in std_logic_vector(15 downto 0);
		ad_in		: in std_logic_vector(7 downto 0);
		iow		 	: in std_logic;
		tx			: out std_logic;
		on_tx 		: out std_logic		 		
);
end entity;

architecture tx of tx8 is

component wri_reg8 is port(
		iow			: in std_logic;
		rst			: in std_logic;
		cs			: in std_logic;
		data_in		: in std_logic_vector(7 downto 0);
		data_out	: out std_logic_vector(7 downto 0)
		);
end component;		

component data_clk is port (
		rst				: in std_logic;
		p1mhz			: in std_logic;
		can_data_clk	: in std_logic;
		data_clk		: out std_logic		
);
end component;
------------------------------
signal cs_data : std_logic;
signal t_data : std_logic_vector(7 downto 0);
---------------------------------
signal data_cnt : integer range 0 to 31;
signal tx_clk : std_logic;
signal en_tx,end_tx : std_logic;
signal t_tx : std_logic; 

constant data_cnt_limit : integer := 12;

begin
cs_data <= '0' when SA=X"c00b" else '1';
u_write_data : wri_reg8 port map(
		iow			=> iow,--: in std_logic;
		rst			=> rst,--: in std_logic;
		cs			=> cs_data,--: in std_logic;
		data_in		=> ad_in,--: in std_logic_vector(7 downto 0);
		data_out	=> t_data--: out std_logic_vector(7 downto 0)
		);
		
on_tx <= '1' when en_tx='1' else '0';
tx <= t_tx; 

u_data_clk : data_clk port map (
		rst				=> rst,--: in std_logic;
		p1mhz			=> p1mhz,--: in std_logic;
		can_data_clk	=> en_tx,--: in std_logic;
		data_clk		=> tx_clk );--: out std_logic--;


process(rst,end_tx,iow,sa)
begin
	if rst='0' or end_tx='1' then
		en_tx <= '0';
	else
		if rising_edge(iow) then
			if sa=x"c00b" then
				en_tx <= '1';
			end if;	
		end if;
	end if;			 
end process;

process(rst,data_cnt,en_tx,tx_clk)
begin
	if rst='0' or en_tx = '0' then
		end_tx <= '0';
	else
		if rising_edge(tx_clk) then
			if data_cnt = data_cnt_limit then
				end_tx <= '1';	
			end if;
		end if;
	end if;			
end process;

process(rst,t_data,data_cnt,en_tx,t_tx)
begin
	if rst='0' then
		t_tx <= '1';
	elsif data_cnt = 1 and en_tx='1' then
		t_tx <= '0';
	elsif data_cnt >= 2 and data_cnt <= 9 and en_tx='1' then 	
		t_tx <= t_data(data_cnt-2);
	elsif data_cnt >= 10 then
		t_tx <= '1';
	else	
		t_tx <= '1';
	end if;		
end process;

process(rst,tx_clk,data_cnt,en_tx)
begin
	if rst='0' or en_tx='0' then
		data_cnt <= 0;
	else 
		if rising_edge(tx_clk) then	
			if en_tx='1' then
				if data_cnt < data_cnt_limit then
					data_cnt <= data_cnt + 1;
				end if;
			end if;
		end if;
	end if;				
end process;



end architecture;